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	8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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							@ -229,10 +229,12 @@ endif
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ifeq ($(CPU),mpc85xx)
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LIBS += drivers/qe/qe.a
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LIBS += cpu/mpc8xxx/ddr/libddr.a
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LIBS += cpu/mpc8xxx/lib8xxx.a
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TAG_SUBDIRS += cpu/mpc8xxx
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endif
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ifeq ($(CPU),mpc86xx)
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LIBS += cpu/mpc8xxx/ddr/libddr.a
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LIBS += cpu/mpc8xxx/lib8xxx.a
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TAG_SUBDIRS += cpu/mpc8xxx
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endif
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LIBS += drivers/rtc/librtc.a
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@ -1,5 +1,5 @@
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/*
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 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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 * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
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 * (C) Copyright 2002, 2003 Motorola Inc.
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 * Xianghua Xiao (X.Xiao@motorola.com)
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 *
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@ -29,58 +29,12 @@
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cpu_type cpu_type_list [] = {
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	CPU_TYPE_ENTRY(8533, 8533),
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	CPU_TYPE_ENTRY(8533, 8533_E),
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	CPU_TYPE_ENTRY(8535, 8535),
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	CPU_TYPE_ENTRY(8535, 8535_E),
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	CPU_TYPE_ENTRY(8536, 8536),
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	CPU_TYPE_ENTRY(8536, 8536_E),
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	CPU_TYPE_ENTRY(8540, 8540),
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	CPU_TYPE_ENTRY(8541, 8541),
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	CPU_TYPE_ENTRY(8541, 8541_E),
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	CPU_TYPE_ENTRY(8543, 8543),
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	CPU_TYPE_ENTRY(8543, 8543_E),
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	CPU_TYPE_ENTRY(8544, 8544),
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	CPU_TYPE_ENTRY(8544, 8544_E),
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	CPU_TYPE_ENTRY(8545, 8545),
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	CPU_TYPE_ENTRY(8545, 8545_E),
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	CPU_TYPE_ENTRY(8547, 8547_E),
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	CPU_TYPE_ENTRY(8548, 8548),
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	CPU_TYPE_ENTRY(8548, 8548_E),
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	CPU_TYPE_ENTRY(8555, 8555),
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	CPU_TYPE_ENTRY(8555, 8555_E),
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	CPU_TYPE_ENTRY(8560, 8560),
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	CPU_TYPE_ENTRY(8567, 8567),
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	CPU_TYPE_ENTRY(8567, 8567_E),
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	CPU_TYPE_ENTRY(8568, 8568),
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	CPU_TYPE_ENTRY(8568, 8568_E),
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	CPU_TYPE_ENTRY(8569, 8569),
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	CPU_TYPE_ENTRY(8569, 8569_E),
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	CPU_TYPE_ENTRY(8572, 8572),
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	CPU_TYPE_ENTRY(8572, 8572_E),
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	CPU_TYPE_ENTRY(P2020, P2020),
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	CPU_TYPE_ENTRY(P2020, P2020_E),
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};
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struct cpu_type *identify_cpu(u32 ver)
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{
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	int i;
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	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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		if (cpu_type_list[i].soc_ver == ver)
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			return &cpu_type_list[i];
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	return NULL;
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}
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int checkcpu (void)
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{
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	sys_info_t sysinfo;
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@ -329,28 +283,6 @@ void upmconfig (uint upm, uint * table, uint size)
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	out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
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}
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/*
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 * Initializes on-chip ethernet controllers.
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 * to override, implement board_eth_init()
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 */
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_ETHER_ON_FCC)
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	fec_initialize(bis);
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#endif
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#if defined(CONFIG_UEC_ETH)
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	uec_standard_init(bis);
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#endif
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
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	tsec_standard_init(bis);
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#endif
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	return 0;
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}
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/*
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 * Initializes on-chip MMC controllers.
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 * to override, implement board_mmc_init()
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@ -1,5 +1,5 @@
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/*
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 * Copyright 2006 Freescale Semiconductor
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 * Copyright 2006,2009 Freescale Semiconductor, Inc.
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 * Jeff Brown
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 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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 *
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@ -28,25 +28,8 @@
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mpc86xx.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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struct cpu_type cpu_type_list [] = {
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	CPU_TYPE_ENTRY(8610, 8610),
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	CPU_TYPE_ENTRY(8641, 8641),
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	CPU_TYPE_ENTRY(8641D, 8641D),
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};
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struct cpu_type *identify_cpu(u32 ver)
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{
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	int i;
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	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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		if (cpu_type_list[i].soc_ver == ver)
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			return &cpu_type_list[i];
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	return NULL;
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}
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/*
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 * Default board reset function
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 */
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@ -209,16 +192,3 @@ void mpc86xx_reginfo(void)
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	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
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}
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/*
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 * Initializes on-chip ethernet controllers.
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 * to override, implement board_eth_init()
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 */
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_TSEC_ENET)
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	tsec_standard_init(bis);
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#endif
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	return 0;
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}
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										25
									
								
								cpu/mpc8xxx/Makefile
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										25
									
								
								cpu/mpc8xxx/Makefile
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,25 @@
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#
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# Copyright 2009 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# Version 2 as published by the Free Software Foundation.
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#
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include $(TOPDIR)/config.mk
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LIB	= $(obj)lib8xxx.a
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COBJS-y	+= cpu.o
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SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
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all:	$(obj).depend $(LIB)
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$(LIB):	$(OBJS)
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	$(AR) $(ARFLAGS) $@ $(OBJS)
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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										106
									
								
								cpu/mpc8xxx/cpu.c
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										106
									
								
								cpu/mpc8xxx/cpu.c
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,106 @@
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/*
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 * Copyright 2009 Freescale Semiconductor, Inc.
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 *
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 * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
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 * Basically this file contains cpu specific common code for 85xx/86xx
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 * processors.
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 * See file CREDITS for list of people who contributed to this
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 * project.
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cpu_type cpu_type_list [] = {
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#if defined(CONFIG_MPC85xx)
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	CPU_TYPE_ENTRY(8533, 8533),
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	CPU_TYPE_ENTRY(8533, 8533_E),
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	CPU_TYPE_ENTRY(8535, 8535),
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	CPU_TYPE_ENTRY(8535, 8535_E),
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	CPU_TYPE_ENTRY(8536, 8536),
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	CPU_TYPE_ENTRY(8536, 8536_E),
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	CPU_TYPE_ENTRY(8540, 8540),
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	CPU_TYPE_ENTRY(8541, 8541),
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	CPU_TYPE_ENTRY(8541, 8541_E),
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	CPU_TYPE_ENTRY(8543, 8543),
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	CPU_TYPE_ENTRY(8543, 8543_E),
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	CPU_TYPE_ENTRY(8544, 8544),
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	CPU_TYPE_ENTRY(8544, 8544_E),
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	CPU_TYPE_ENTRY(8545, 8545),
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	CPU_TYPE_ENTRY(8545, 8545_E),
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	CPU_TYPE_ENTRY(8547, 8547_E),
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	CPU_TYPE_ENTRY(8548, 8548),
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	CPU_TYPE_ENTRY(8548, 8548_E),
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	CPU_TYPE_ENTRY(8555, 8555),
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	CPU_TYPE_ENTRY(8555, 8555_E),
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	CPU_TYPE_ENTRY(8560, 8560),
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	CPU_TYPE_ENTRY(8567, 8567),
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	CPU_TYPE_ENTRY(8567, 8567_E),
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	CPU_TYPE_ENTRY(8568, 8568),
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	CPU_TYPE_ENTRY(8568, 8568_E),
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	CPU_TYPE_ENTRY(8569, 8569),
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	CPU_TYPE_ENTRY(8569, 8569_E),
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	CPU_TYPE_ENTRY(8572, 8572),
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	CPU_TYPE_ENTRY(8572, 8572_E),
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	CPU_TYPE_ENTRY(P2020, P2020),
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	CPU_TYPE_ENTRY(P2020, P2020_E),
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#elif defined(CONFIG_MPC86xx)
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	CPU_TYPE_ENTRY(8610, 8610),
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	CPU_TYPE_ENTRY(8641, 8641),
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	CPU_TYPE_ENTRY(8641D, 8641D),
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#endif
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};
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struct cpu_type *identify_cpu(u32 ver)
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{
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	int i;
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	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
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		if (cpu_type_list[i].soc_ver == ver)
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			return &cpu_type_list[i];
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	}
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	return NULL;
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}
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/*
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 * Initializes on-chip ethernet controllers.
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 * to override, implement board_eth_init()
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 */
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_ETHER_ON_FCC)
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	fec_initialize(bis);
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#endif
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#if defined(CONFIG_UEC_ETH)
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	uec_standard_init(bis);
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#endif
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
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	tsec_standard_init(bis);
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#endif
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	return 0;
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}
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