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board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop

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CPLD's system reset register on P1/P2 RDB boards is not autocleared after
flipping it. If this register is set to one in 100ms after reset starts
then CPLD triggers another CPU reset.

This means that trying to reset board via CPLD system reset register cause
reboot loop. To prevent this reboot loop, the only workaround is to try to
clear CPLD's system reset register as early as possible. U-Boot is already
doing it in its board_early_init_f() function, which seems to be enough as
register is cleared prior CPLD triggers another reset.

But board_early_init_f() is not called from SPL and therefore usage of SPL
can cause reboot loop.

To prevent reboot loop when using SPL, call board_early_init_f() function
in SPL too. For accessing CPLD memory space it is needed to have CPLD entry
in TLB.

With this change it is possible to trigger board reset via CPLD's system
reset register on P2020 RDB board.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Pali Rohár 2022-08-01 15:31:43 +02:00 committed by Peng Fan
parent 5025224fad
commit 1f90be6f34
3 changed files with 20 additions and 1 deletions
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13
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -97,6 +97,19 @@ void board_cpld_init(void)
out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->status_led, CPLD_STATUS_LED);
out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
out_8(&cpld_data->fxs_led, CPLD_FXS_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
/*
* CPLD's system reset register on P1/P2 RDB boards is not autocleared
* after flipping it. If this register is set to one then CPLD triggers
* reset of CPU in few ms.
*
* CPLD does not trigger reset of CPU for 100ms after the last reset.
*
* This means that trying to reset board via CPLD system reset register
* cause reboot loop. To prevent this reboot loop, the only workaround
* is to try to clear CPLD's system reset register as early as possible
* and it has to be done in 100ms since the last start of reset.
*/
out_8(&cpld_data->system_rst, CPLD_SYS_RST); out_8(&cpld_data->system_rst, CPLD_SYS_RST);
} }

6
board/freescale/p1_p2_rdb_pc/spl.c
View File

@ -31,6 +31,12 @@ void board_init_f(ulong bootflag)
u32 plat_ratio, bus_clk; u32 plat_ratio, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds
* reboot loop due to broken CPLD state machine for reset line.
*/
board_early_init_f();
console_init_f(); console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */ /* Set pmuxcr to allow both i2c1 and i2c2 */

2
board/freescale/p1_p2_rdb_pc/tlb.c
View File

@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1), 0, 5, BOOKE_PAGESZ_1M, 1),
#endif #endif
#endif /* not SPL */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1), 0, 6, BOOKE_PAGESZ_1M, 1),
#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE #ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */ /* *I*G - NAND */