ram: sunxi: Add Allwinner D1 DRAM driver

Signed-off-by: Samuel Holland <samuel@sholland.org>

drivers/ram/Kconfig

@@ -101,3 +101,4 @@ source "drivers/ram/rockchip/Kconfig"
 source "drivers/ram/sifive/Kconfig"
 source "drivers/ram/stm32mp1/Kconfig"
 source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/sunxi/Kconfig"

drivers/ram/Makefile

@@ -20,5 +20,6 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
 obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
 
 obj-$(CONFIG_RAM_SIFIVE) += sifive/
+obj-$(CONFIG_RAM_SUNXI) += sunxi/
 
 obj-$(CONFIG_ARCH_OCTEON) += octeon/

drivers/ram/sunxi/Kconfig

@@ -0,0 +1,6 @@
+config RAM_SUNXI
+	bool "Ram drivers support for sunxi SoCs"
+	depends on RAM && BOARD_SUNXI
+	default y
+	help
+	  This enables support for ram drivers of sunxi SoCs.

drivers/ram/sunxi/Makefile

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_RAM_SUNXI) += mctl_hal-sun20iw1p1.o

drivers/ram/sunxi/dram_v2.h

@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2007-2013
+* SPDX-License-Identifier:	GPL-2.0+
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef  __dram_head_h__
+#define  __dram_head_h__
+
+struct dram_para_t
+{
+	//normal configuration
+	unsigned int        dram_clk;
+	unsigned int        dram_type;		//dram_type			DDR2: 2				DDR3: 3		LPDDR2: 6	LPDDR3: 7	DDR3L: 31
+	//unsigned int        lpddr2_type;	//LPDDR2 type		S4:0	S2:1 	NVM:2
+	unsigned int        dram_zq;		//do not need
+	unsigned int		dram_odt_en;
+
+	//control configuration
+	unsigned int		dram_para1;
+	unsigned int		dram_para2;
+
+	//timing configuration
+	unsigned int		dram_mr0;
+	unsigned int		dram_mr1;
+	unsigned int		dram_mr2;
+	unsigned int		dram_mr3;
+	unsigned int		dram_tpr0;	//DRAMTMG0
+	unsigned int		dram_tpr1;	//DRAMTMG1
+	unsigned int		dram_tpr2;	//DRAMTMG2
+	unsigned int		dram_tpr3;	//DRAMTMG3
+	unsigned int		dram_tpr4;	//DRAMTMG4
+	unsigned int		dram_tpr5;	//DRAMTMG5
+   	unsigned int		dram_tpr6;	//DRAMTMG8
+	//reserved for future use
+	unsigned int		dram_tpr7;
+	unsigned int		dram_tpr8;
+	unsigned int		dram_tpr9;
+	unsigned int		dram_tpr10;
+	unsigned int		dram_tpr11;
+	unsigned int		dram_tpr12;
+	unsigned int		dram_tpr13;
+
+};
+
+#endif

drivers/ram/sunxi/sdram.h

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * dram_para1 bits:
+ *  16-19 = page size
+ *  20-27 = row count
+ *     28 = banks 4 or 8
+ *
+ * dram_para2 bits:
+ *      0 = DQ width
+ *      4 = CS1 control
+ *   8-11 = rank flags? bit 8 = ranks differ in config
+ *  12-13 = rank
+ */
+
+/* MC_WORK_MODE bits
+ *   0- 1 = ranks code
+ *   2- 3 = banks, log2 - 2		 2	 3	 2
+ *   4- 7 = row width, log2 - 1		 16	11	11
+ *   8-11 = page size, log2 - 3		 9	 9	13
+ *  12-15 = DQ width (or 12-14?)
+ *  16-18 = dram type (2=DDR2, 3=DDR3, 6=LPDDR2, 7=LPDDR3)
+ *     19 = 2T or 1T
+ *  23-24 = ranks code (again?)
+ */
+
+#define DRAM_MR0	((void*)0x3103030)
+#define DRAM_MR1	((void*)0x3103034)
+#define DRAM_MR2	((void*)0x3103038)
+#define DRAM_MR3	((void*)0x310303c)
+
+#define DRAMTMG0	((void*)0x3103058)
+#define DRAMTMG1	((void*)0x310305c)
+#define DRAMTMG2	((void*)0x3103060)
+#define DRAMTMG3	((void*)0x3103064)
+#define DRAMTMG4	((void*)0x3103068)
+#define DRAMTMG5	((void*)0x310306c)
+#define DRAMTMG6	((void*)0x3103070)
+#define DRAMTMG7	((void*)0x3103074)
+#define DRAMTMG8	((void*)0x3103078)
+
+#define PITMG0		((void*)0x3103080)
+#define PTR3           	((void*)0x3103050)
+#define PTR4           	((void*)0x3103054)
+#define RFSHTMG        	((void*)0x3103090)
+#define RFSHCTL1       	((void*)0x3103094)