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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/fsl_pci: Fix device tree fixups for newer platforms
This commit is contained in:
Wolfgang Denk 2011-06-01 22:01:07 +02:00
commit 2130b03309
3 changed files with 19 additions and 1 deletions
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5
README
View File

@ -363,6 +363,11 @@ The following options need to be configured:
system clock. On most PQ3 devices this is 8, on newer QorIQ
devices it can be 16 or 32. The ratio varies from SoC to Soc.
CONFIG_SYS_FSL_PCIE_COMPAT
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO

9
arch/powerpc/include/asm/config_mpc85xx.h
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@ -96,6 +96,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_P1011)
@ -175,6 +176,7 @@
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#elif defined(CONFIG_P1020)
#define CONFIG_MAX_CPUS 2
@ -216,6 +218,7 @@
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_P1024)
@ -265,6 +268,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -280,6 +284,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -291,6 +296,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
@ -305,6 +311,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@ -330,6 +337,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -345,6 +353,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111

6
arch/powerpc/include/asm/fsl_pci.h
View File

@ -233,7 +233,7 @@ int fsl_pcie_init_board(int busno);
#if !defined(CONFIG_PCI)
#define FT_FSL_PCI_SETUP
#elif defined(CONFIG_FSL_CORENET)
#define FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
#define FT_FSL_PCI_SETUP \
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP; \
@ -242,7 +242,11 @@ int fsl_pcie_init_board(int busno);
#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
#elif defined(CONFIG_MPC85xx)
#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
#else
#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
#endif
#define FT_FSL_PCI_SETUP \
FT_FSL_PCI1_SETUP; \
FT_FSL_PCI2_SETUP; \