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arm, imx6, i2c: add I2C4 for MX6DL

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add I2C4 modul for MX6DL based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher 2015-05-18 10:56:24 +02:00 committed by Stefano Babic
parent ab87fc6bbd
commit 21a26940f9
5 changed files with 32 additions and 12 deletions
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33
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -140,23 +140,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
#endif
#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0 - 2 */
/* i2c_num can be from 0 - 3 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u32 reg;
u32 mask;
if (i2c_num > 2)
if (i2c_num > 3)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK
<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
reg = __raw_readl(&imx_ccm->CCGR2);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
if (i2c_num < 3) {
mask = MXC_CCM_CCGR_CG_MASK
<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+ (i2c_num << 1));
reg = __raw_readl(&imx_ccm->CCGR2);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
mask = MXC_CCM_CCGR_CG_MASK
<< (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
reg = __raw_readl(&imx_ccm->CCGR1);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR1);
}
return 0;
}
#endif

5
arch/arm/imx-common/i2c-mxv7.c
View File

@ -67,9 +67,12 @@ static void * const i2c_bases[] = {
#ifdef I2C3_BASE_ADDR
(void *)I2C3_BASE_ADDR,
#endif
#ifdef I2C4_BASE_ADDR
(void *)I2C4_BASE_ADDR,
#endif
};
/* i2c_index can be from 0 - 2 */
/* i2c_index can be from 0 - 3 */
int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p)
{

2
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@ -592,6 +592,8 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14

1
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -277,6 +277,7 @@
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)

3
drivers/i2c/mxc_i2c.c
View File

@ -517,6 +517,9 @@ static struct mxc_i2c_bus mxc_i2c_buses[] = {
{ 0, I2C1_BASE_ADDR },
{ 1, I2C2_BASE_ADDR },
{ 2, I2C3_BASE_ADDR },
#if defined(CONFIG_MX6DL)
{ 3, I2C4_BASE_ADDR },
#endif
#elif defined(CONFIG_LS102XA)
{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },