random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-11-03 21:48:15 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch '2020-09-09-assorted-soc-updates' into next

Browse Source 
- Assorted improvements for MediaTek, Broadcom NS3 and ASPEED SoCs.
This commit is contained in:
Tom Rini 2020-09-10 14:37:45 -04:00
commit 23e92c124b
17 changed files with 428 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -237,6 +237,7 @@ M: Luka Kovacic <luka.kovacic@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/mach-ipq40xx/
F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
@ -1005,6 +1006,10 @@ F: arch/arm/dts/ns3-board.dts
F: arch/arm/dts/ns3.dtsi
F: arch/arm/cpu/armv8/bcmns3
F: arch/arm/include/asm/arch-bcmns3/
F: cmd/broadcom/Makefile
F: cmd/broadcom/chimp_boot.c
F: cmd/broadcom/nitro_image_load.c
F: cmd/broadcom/chimp_handshake.c
TDA19988 HDMI ENCODER
M: Liviu Dudau <liviu.dudau@foss.arm.com>

2
arch/arm/dts/Makefile
View File

@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb

23
arch/arm/dts/ast2500-u-boot.dtsi
View File

@ -1,4 +1,5 @@
#include <dt-bindings/clock/ast2500-scu.h>
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/reset/ast2500-reset.h>
#include "ast2500.dtsi"
@ -25,7 +26,7 @@
reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst AST_RESET_SDRAM>;
};
@ -39,7 +40,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>;
};
@ -47,7 +48,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>;
};
};
@ -56,23 +57,23 @@
};
&uart1 {
clocks = <&scu PCLK_UART1>;
clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
};
&uart2 {
clocks = <&scu PCLK_UART2>;
clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
};
&uart3 {
clocks = <&scu PCLK_UART3>;
clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
};
&uart4 {
clocks = <&scu PCLK_UART4>;
clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
};
&uart5 {
clocks = <&scu PCLK_UART5>;
clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
};
&timer {
@ -80,9 +81,9 @@
};
&mac0 {
clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
};
&mac1 {
clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
};

2
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
View File

@ -19,7 +19,7 @@
#include <asm/arch/wdt.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/ast2500-scu.h>
#include <dt-bindings/clock/aspeed-clock.h>
/* These configuration parameters are taken from Aspeed SDK */
#define DDR4_MR46_MODE 0x08000000

7
board/broadcom/bcmns3/Kconfig
View File

@ -12,4 +12,11 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "bcm_ns3"
config CMD_BCM_EXT_UTILS
bool "Enable Broadcom-specific U-Boot commands"
default y
help
Enable Broadcom specific U-Boot commands such as error log setup
command or any other commands specific to NS3 platform.
endif

17
board/broadcom/bcmns3/ns3.c
View File

@ -12,6 +12,7 @@
#include <asm/armv8/mmu.h>
#include <asm/arch-bcmns3/bl33_info.h>
#include <dt-bindings/memory/bcm-ns3-mc.h>
#include <broadcom/chimp.h>
/* Default reset-level = 3 and strap-val = 0 */
#define L3_RESET 30
@ -210,8 +211,24 @@ void reset_cpu(ulong level)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *fdt, struct bd_info *bd)
{
u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
gic_lpi_tables_init();
/*
* Check for chimp handshake status.
* Zero timeout value will actually fall to default timeout.
*
* System boot is independent of chimp handshake.
* chimp handshake failure is not a catastrophic error.
* Hence continue booting if chimp handshake fails.
*/
chimp_handshake_status_optee(0, &chimp_hs);
if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
printf("ChiMP handshake successful\n");
else
printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
return mem_info_parse_fixup(fdt);
}
#endif /* CONFIG_OF_BOARD_SETUP */

2
cmd/Makefile
View File

@ -197,6 +197,8 @@ obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o
# core command
obj-y += nvedit.o
obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/
obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")

6
cmd/broadcom/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright 2020 Broadcom
obj-y += chimp_boot.o
obj-y += nitro_image_load.o
obj-y += chimp_handshake.o

37
cmd/broadcom/chimp_boot.c Normal file
View File

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Broadcom
*/
#include <common.h>
#include <command.h>
#include <broadcom/chimp.h>
static int do_chimp_fastboot_secure(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
u32 health = 0;
if (chimp_health_status_optee(&health)) {
pr_err("Chimp health command fail\n");
return CMD_RET_FAILURE;
}
if (health == BCM_CHIMP_RUNNIG_GOOD) {
printf("skip fastboot...\n");
return CMD_RET_SUCCESS;
}
if (chimp_fastboot_optee()) {
pr_err("Failed to load secure ChiMP image\n");
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
U_BOOT_CMD
(chimp_ld_secure, 1, 0, do_chimp_fastboot_secure,
"Invoke chimp fw load via optee",
"chimp_ld_secure\n"
);

33
cmd/broadcom/chimp_handshake.c Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Broadcom
*/
#include <common.h>
#include <command.h>
#include <broadcom/chimp.h>
/* This command should be called after loading the nitro binaries */
static int do_chimp_hs(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int ret = CMD_RET_USAGE;
u32 hstatus;
/* Returns 1, if handshake call is success */
if (chimp_handshake_status_optee(0, &hstatus))
ret = CMD_RET_SUCCESS;
if (hstatus == CHIMP_HANDSHAKE_SUCCESS)
printf("ChiMP Handshake successful\n");
else
printf("ERROR: ChiMP Handshake status 0x%x\n", hstatus);
return ret;
}
U_BOOT_CMD
(chimp_hs, 1, 1, do_chimp_hs,
"Verify the Chimp handshake",
"chimp_hs\n"
);

125
cmd/broadcom/nitro_image_load.c Normal file
View File

@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Broadcom
*/
#include <common.h>
#include <command.h>
#define FW_IMAGE_SIG 0xff123456
#define CFG_IMAGE_SIG 0xcf54321a
/*
* structure for bin file
* signature: fw itb file
* size: fw itb file
* signature: NS3 config file
* size: NS3 config file
* Data: fw itb file
* ............................
* ............................
* Data: NS3 config file
* ............................
* ............................
*/
static struct img_header {
u32 bin_sig;
u32 bin_size;
u32 cfg1_sig;
u32 cfg1_size;
} *img_header;
static int env_set_val(const char *varname, ulong val)
{
int ret;
ret = env_set_hex(varname, val);
if (ret)
pr_err("Failed to %s env var\n", varname);
return ret;
}
static int do_spi_images_addr(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
uintptr_t images_load_addr;
uintptr_t spi_load_addr;
u32 len;
u32 spi_data_offset = sizeof(struct img_header);
if (argc != 3)
return CMD_RET_USAGE;
/* convert command parameter to fastboot address (base 16), i.e. hex */
images_load_addr = simple_strtoul(argv[1], NULL, 16);
if (!images_load_addr) {
pr_err("Invalid load address\n");
return CMD_RET_USAGE;
}
spi_load_addr = simple_strtoul(argv[2], NULL, 16);
if (!spi_load_addr) {
pr_err("Invalid spi load address\n");
return CMD_RET_USAGE;
}
img_header = (struct img_header *)images_load_addr;
if (img_header->bin_sig != FW_IMAGE_SIG) {
pr_err("Invalid Nitro bin file\n");
goto error;
}
if (env_set_val("spi_nitro_fw_itb_start_addr", 0))
goto error;
if (env_set_val("spi_nitro_fw_itb_len", 0))
goto error;
if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr", 0))
goto error;
if (env_set_val("spi_nitro_fw_ns3_cfg_len", 0))
goto error;
len = img_header->bin_size;
if (env_set_val("spi_nitro_fw_itb_start_addr",
(spi_load_addr + spi_data_offset)))
goto error;
if (env_set_val("spi_nitro_fw_itb_len", img_header->bin_size))
goto error;
spi_data_offset += len;
if (img_header->cfg1_sig == CFG_IMAGE_SIG) {
len = img_header->cfg1_size;
if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr",
(spi_load_addr + spi_data_offset)))
goto error;
if (env_set_val("spi_nitro_fw_ns3_cfg_len", len))
goto error;
spi_data_offset += len;
}
/* disable secure boot */
if (env_set_val("nitro_fastboot_secure", 0))
goto error;
return CMD_RET_SUCCESS;
error:
return CMD_RET_FAILURE;
}
U_BOOT_CMD
(spi_nitro_images_addr, 3, 1, do_spi_images_addr,
"Load the bnxt bin header and sets envs ",
"spi_nitro_images_addr <load_addr> <spi_base_addr>\n"
);

40
drivers/clk/aspeed/clk_ast2500.c
View File

@ -10,7 +10,7 @@
#include <asm/io.h>
#include <asm/arch/scu_ast2500.h>
#include <dm/lists.h>
#include <dt-bindings/clock/ast2500-scu.h>
#include <dt-bindings/clock/aspeed-clock.h>
#include <linux/delay.h>
#include <linux/err.h>
@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
ulong rate;
switch (clk->id) {
case PLL_HPLL:
case ARMCLK:
case ASPEED_CLK_HPLL:
/*
* This ignores dynamic/static slowdown of ARMCLK and may
* be inaccurate.
@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_hpll_rate(clkin,
readl(&priv->scu->h_pll_param));
break;
case MCLK_DDR:
case ASPEED_CLK_MPLL:
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
case BCLK_PCLK:
case ASPEED_CLK_APB:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_PCLK_DIV_MASK)
@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
case BCLK_SDCLK:
case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_SDCLK_DIV_MASK)
@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
case PCLK_UART1:
case ASPEED_CLK_GATE_UART1CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
case PCLK_UART2:
case ASPEED_CLK_GATE_UART2CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 2);
break;
case PCLK_UART3:
case ASPEED_CLK_GATE_UART3CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 3);
break;
case PCLK_UART4:
case ASPEED_CLK_GATE_UART4CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 4);
break;
case PCLK_UART5:
case ASPEED_CLK_GATE_UART5CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 5);
break;
default:
@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
ulong new_rate;
switch (clk->id) {
case PLL_MPLL:
case MCLK_DDR:
case ASPEED_CLK_MPLL:
new_rate = ast2500_configure_ddr(priv->scu, rate);
break;
case PLL_D2PLL:
case ASPEED_CLK_D2PLL:
new_rate = ast2500_configure_d2pll(priv->scu, rate);
break;
default:
@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk)
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case BCLK_SDCLK:
case ASPEED_CLK_SDIO:
if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
ast_scu_unlock(priv->scu);
@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk)
* configured based on whether RGMII or RMII mode has been selected
* through hardware strapping.
*/
case PCLK_MAC1:
case ASPEED_CLK_GATE_MAC1CLK:
ast2500_configure_mac(priv->scu, 1);
break;
case PCLK_MAC2:
case ASPEED_CLK_GATE_MAC2CLK:
ast2500_configure_mac(priv->scu, 2);
break;
case PLL_D2PLL:
case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
default:
@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
{
struct ast2500_clk_priv *priv = dev_get_priv(dev);
priv->scu = dev_read_addr_ptr(dev);
if (!priv->scu)
return -EINVAL;
priv->scu = devfdt_get_addr_ptr(dev);
if (IS_ERR(priv->scu))
return PTR_ERR(priv->scu);
return 0;
}

19
drivers/pci/pcie_mediatek.c
View File

@ -443,29 +443,36 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
err = clk_enable(&port->sys_ck);
if (err)
goto exit;
goto err_sys_clk;
err = reset_assert(&port->reset);
if (err)
goto exit;
goto err_reset;
err = reset_deassert(&port->reset);
if (err)
goto exit;
goto err_reset;
err = generic_phy_init(&port->phy);
if (err)
goto exit;
goto err_phy_init;
err = generic_phy_power_on(&port->phy);
if (err)
goto exit;
goto err_phy_on;
if (!mtk_pcie_startup_port(port))
return;
pr_err("Port%d link down\n", port->slot);
exit:
generic_phy_power_off(&port->phy);
err_phy_on:
generic_phy_exit(&port->phy);
err_phy_init:
err_reset:
clk_disable(&port->sys_ck);
err_sys_clk:
mtk_pcie_port_free(port);
}

12
include/broadcom/chimp.h
View File

@ -9,6 +9,18 @@
#include <linux/compiler.h>
/*
* Chimp binary has health status like initialization complete,
* crash or running fine
*/
#define BCM_CHIMP_RUNNIG_GOOD 0x8000
enum {
CHIMP_HANDSHAKE_SUCCESS = 0,
CHIMP_HANDSHAKE_WAIT_ERROR,
CHIMP_HANDSHAKE_WAIT_TIMEOUT,
};
/**
* chimp_fastboot_optee() - api to load bnxt firmware
*

42
include/dt-bindings/clock/aspeed-clock.h Normal file
View File

@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0
#define ASPEED_CLK_GATE_ECLK 0
#define ASPEED_CLK_GATE_GCLK 1
#define ASPEED_CLK_GATE_MCLK 2
#define ASPEED_CLK_GATE_VCLK 3
#define ASPEED_CLK_GATE_BCLK 4
#define ASPEED_CLK_GATE_DCLK 5
#define ASPEED_CLK_GATE_REFCLK 6
#define ASPEED_CLK_GATE_USBPORT2CLK 7
#define ASPEED_CLK_GATE_LCLK 8
#define ASPEED_CLK_GATE_USBUHCICLK 9
#define ASPEED_CLK_GATE_D1CLK 10
#define ASPEED_CLK_GATE_YCLK 11
#define ASPEED_CLK_GATE_USBPORT1CLK 12
#define ASPEED_CLK_GATE_UART1CLK 13
#define ASPEED_CLK_GATE_UART2CLK 14
#define ASPEED_CLK_GATE_UART5CLK 15
#define ASPEED_CLK_GATE_ESPICLK 16
#define ASPEED_CLK_GATE_MAC1CLK 17
#define ASPEED_CLK_GATE_MAC2CLK 18
#define ASPEED_CLK_GATE_RSACLK 19
#define ASPEED_CLK_GATE_UART3CLK 20
#define ASPEED_CLK_GATE_UART4CLK 21
#define ASPEED_CLK_GATE_SDCLK 22
#define ASPEED_CLK_GATE_LHCCLK 23
#define ASPEED_CLK_HPLL 24
#define ASPEED_CLK_AHB 25
#define ASPEED_CLK_APB 26
#define ASPEED_CLK_UART 27
#define ASPEED_CLK_SDIO 28
#define ASPEED_CLK_ECLK 29
#define ASPEED_CLK_ECLK_MUX 30
#define ASPEED_CLK_LHCLK 31
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
#define ASPEED_CLK_24M 35
#define ASPEED_CLK_MAC1RCLK 36
#define ASPEED_CLK_MAC2RCLK 37
#define ASPEED_CLK_DPLL 38
#define ASPEED_CLK_D2PLL 39

30
include/dt-bindings/clock/ast2500-scu.h
View File

@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Google Inc.
*/
/* Core Clocks */
#define PLL_HPLL 1
#define PLL_DPLL 2
#define PLL_D2PLL 3
#define PLL_MPLL 4
#define ARMCLK 5
/* Bus Clocks, derived from core clocks */
#define BCLK_PCLK 101
#define BCLK_LHCLK 102
#define BCLK_MACCLK 103
#define BCLK_SDCLK 104
#define BCLK_ARMCLK 105
#define MCLK_DDR 201
/* Special clocks */
#define PCLK_UART1 501
#define PCLK_UART2 502
#define PCLK_UART3 503
#define PCLK_UART4 504
#define PCLK_UART5 505
#define PCLK_MAC1 506
#define PCLK_MAC2 507

96
include/dt-bindings/clock/qcom,ipq4019-gcc.h Normal file
View File

@ -0,0 +1,96 @@
/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef __QCOM_CLK_IPQ4019_H__
#define __QCOM_CLK_IPQ4019_H__
#define GCC_DUMMY_CLK 0
#define AUDIO_CLK_SRC 1
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5
#define BLSP1_UART1_APPS_CLK_SRC 6
#define BLSP1_UART2_APPS_CLK_SRC 7
#define GCC_USB3_MOCK_UTMI_CLK_SRC 8
#define GCC_APPS_CLK_SRC 9
#define GCC_APPS_AHB_CLK_SRC 10
#define GP1_CLK_SRC 11
#define GP2_CLK_SRC 12
#define GP3_CLK_SRC 13
#define SDCC1_APPS_CLK_SRC 14
#define FEPHY_125M_DLY_CLK_SRC 15
#define WCSS2G_CLK_SRC 16
#define WCSS5G_CLK_SRC 17
#define GCC_APSS_AHB_CLK 18
#define GCC_AUDIO_AHB_CLK 19
#define GCC_AUDIO_PWM_CLK 20
#define GCC_BLSP1_AHB_CLK 21
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
#define GCC_BLSP1_UART1_APPS_CLK 26
#define GCC_BLSP1_UART2_APPS_CLK 27
#define GCC_DCD_XO_CLK 28
#define GCC_GP1_CLK 29
#define GCC_GP2_CLK 30
#define GCC_GP3_CLK 31
#define GCC_BOOT_ROM_AHB_CLK 32
#define GCC_CRYPTO_AHB_CLK 33
#define GCC_CRYPTO_AXI_CLK 34
#define GCC_CRYPTO_CLK 35
#define GCC_ESS_CLK 36
#define GCC_IMEM_AXI_CLK 37
#define GCC_IMEM_CFG_AHB_CLK 38
#define GCC_PCIE_AHB_CLK 39
#define GCC_PCIE_AXI_M_CLK 40
#define GCC_PCIE_AXI_S_CLK 41
#define GCC_PCNOC_AHB_CLK 42
#define GCC_PRNG_AHB_CLK 43
#define GCC_QPIC_AHB_CLK 44
#define GCC_QPIC_CLK 45
#define GCC_SDCC1_AHB_CLK 46
#define GCC_SDCC1_APPS_CLK 47
#define GCC_SNOC_PCNOC_AHB_CLK 48
#define GCC_SYS_NOC_125M_CLK 49
#define GCC_SYS_NOC_AXI_CLK 50
#define GCC_TCSR_AHB_CLK 51
#define GCC_TLMM_AHB_CLK 52
#define GCC_USB2_MASTER_CLK 53
#define GCC_USB2_SLEEP_CLK 54
#define GCC_USB2_MOCK_UTMI_CLK 55
#define GCC_USB3_MASTER_CLK 56
#define GCC_USB3_SLEEP_CLK 57
#define GCC_USB3_MOCK_UTMI_CLK 58
#define GCC_WCSS2G_CLK 59
#define GCC_WCSS2G_REF_CLK 60
#define GCC_WCSS2G_RTC_CLK 61
#define GCC_WCSS5G_CLK 62
#define GCC_WCSS5G_REF_CLK 63
#define GCC_WCSS5G_RTC_CLK 64
#define GCC_APSS_DDRPLL_VCO 65
#define GCC_SDCC_PLLDIV_CLK 66
#define GCC_FEPLL_VCO 67
#define GCC_FEPLL125_CLK 68
#define GCC_FEPLL125DLY_CLK 69
#define GCC_FEPLL200_CLK 70
#define GCC_FEPLL500_CLK 71
#define GCC_FEPLL_WCSS2G_CLK 72
#define GCC_FEPLL_WCSS5G_CLK 73
#define GCC_APSS_CPU_PLLDIV_CLK 74
#define GCC_PCNOC_AHB_CLK_SRC 75
#endif