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arm: s5p4418: dm_serial: remove old code / add DEBUG_UART

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Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART
to s5p4418_nanopi2_defconfig.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
This commit is contained in:
Stefan Bosch 2022-12-18 12:26:47 +00:00 committed by Tom Rini
parent 5745de2c9d
commit 28663622cf
4 changed files with 9 additions and 36 deletions
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29
arch/arm/cpu/armv7/s5p4418/cpu.c
View File

@ -13,10 +13,8 @@
#include <asm/io.h>
#include <asm/arch/nexell.h>
#include <asm/arch/clk.h>
#include <asm/arch/reset.h>
#include <asm/arch/tieoff.h>
#include <cpu_func.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
@ -45,39 +43,12 @@ static void cpu_soc_init(void)
nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
}
#ifdef CONFIG_PL011_SERIAL
static void serial_device_init(void)
{
char dev[10];
int id;
sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
struct clk *clk = clk_get((const char *)dev);
/* reset control: Low active ___|--- */
nx_rstcon_setrst(id, RSTCON_ASSERT);
udelay(10);
nx_rstcon_setrst(id, RSTCON_NEGATE);
udelay(10);
/* set clock */
clk_disable(clk);
clk_set_rate(clk, CFG_PL011_CLOCK);
clk_enable(clk);
}
#endif
int arch_cpu_init(void)
{
flush_dcache_all();
cpu_soc_init();
clk_init();
if (IS_ENABLED(CONFIG_PL011_SERIAL))
serial_device_init();
return 0;
}

2
arch/arm/mach-nexell/clock.c
View File

@ -856,7 +856,7 @@ void __init clk_init(void)
}
/* prevent uart clock disable for low step debug message */
#ifndef CONFIG_DEBUG_NX_UART
#ifndef CONFIG_DEBUG_UART
if (peri->dev_name) {
#ifdef CONFIG_BACKLIGHT_PWM
if (!strcmp(peri->dev_name, DEV_NAME_PWM))

6
configs/s5p4418_nanopi2_defconfig
View File

@ -11,12 +11,15 @@ CONFIG_ENV_OFFSET=0x2E0200
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2"
CONFIG_SYS_PROMPT="nanopi2# "
CONFIG_DEBUG_UART_BASE=0xC00A1000
CONFIG_DEBUG_UART_CLOCK=150000000
CONFIG_TARGET_NANOPI2=y
CONFIG_S5P4418_ONEWIRE=y
CONFIG_ROOT_DEV=1
CONFIG_BOOT_PART=1
CONFIG_ROOT_PART=2
CONFIG_SYS_LOAD_ADDR=0x71080000
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x71000000
CONFIG_SYS_MEMTEST_END=0xb0000000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@ -54,7 +57,8 @@ CONFIG_MMC_DW=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_CONS_INDEX=0
CONFIG_DEBUG_UART_PL011=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_DISPLAY=y

8
include/configs/s5p4418_nanopi2.h
View File

@ -76,11 +76,9 @@
/*-----------------------------------------------------------------------
* serial console configuration
*/
#define CFG_PL011_CLOCK 50000000
#define CFG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \
(void *)PHY_BASEADDR_UART1, \
(void *)PHY_BASEADDR_UART2, \
(void *)PHY_BASEADDR_UART3}
/* 150MHz is the clock rate set by SPL (uart0) */
#define CFG_PL011_CLOCK 150000000
/*-----------------------------------------------------------------------
* BACKLIGHT