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clk: imx8mp: Fix 24M and 32k clock

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Fix registration of 24M and 32k clock, those got applied or rebased
incorrectly, so fill in the correct code.

Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
This commit is contained in:
Marek Vasut 2022-04-13 00:41:10 +02:00 committed by Stefano Babic
parent 20bd57e90e
commit 2c6ae0a15f
1 changed files with 11 additions and 1 deletions
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12
drivers/clk/imx/clk-imx8mp.c
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@ -162,7 +162,9 @@ static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }
static int imx8mp_clk_probe(struct udevice *dev) static int imx8mp_clk_probe(struct udevice *dev)
{ {
struct clk osc_24m_clk, osc_32k_clk;
void __iomem *base; void __iomem *base;
int ret;
base = (void *)ANATOP_BASE_ADDR; base = (void *)ANATOP_BASE_ADDR;
@ -215,7 +217,15 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
clk_dm(IMX8MP_CLK_24M, imx_clk_fixed_factor("clock-osc-24m", "osc_24m", 1, 1)); ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
if (ret)
return ret;
clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
ret = clk_get_by_name(dev, "osc_32k", &osc_32k_clk);
if (ret)
return ret;
clk_dm(IMX8MP_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev));
base = dev_read_addr_ptr(dev); base = dev_read_addr_ptr(dev);
if (!base) if (!base)