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arm: gic_v2: Skip gic_init_secure when cpu is not in el3

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This would prevent configuring non-secure regs in case gic security
extensions are not emulated in Qemu.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Sai Pavan Boddu 2022-05-11 10:39:07 +02:00 committed by Tom Rini
parent 012afa83ae
commit 2d25f63cc0
1 changed files with 5 additions and 0 deletions
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5
arch/arm/lib/gic_64.S
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@ -40,6 +40,8 @@ ENTRY(gic_init_secure)
sub w10, w10, #0x1 sub w10, w10, #0x1
cbnz w10, 0b cbnz w10, 0b
#elif defined(CONFIG_GICV2) #elif defined(CONFIG_GICV2)
switch_el x1, 2f, 1f, 1f
2:
mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
ldr w9, [x0, GICD_TYPER] ldr w9, [x0, GICD_TYPER]
@ -141,6 +143,8 @@ ENTRY(gic_init_secure_percpu)
* x0: Distributor Base * x0: Distributor Base
* x1: Cpu Interface Base * x1: Cpu Interface Base
*/ */
switch_el x2, 4f, 5f, 5f
4:
mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
mov w9, #0x1 /* Enable SGI 0 */ mov w9, #0x1 /* Enable SGI 0 */
@ -155,6 +159,7 @@ ENTRY(gic_init_secure_percpu)
mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
str w9, [x1, GICC_PMR] str w9, [x1, GICC_PMR]
#endif #endif
5:
ret ret
ENDPROC(gic_init_secure_percpu) ENDPROC(gic_init_secure_percpu)