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rockchip: clk: Add rv1108 SARADC clock support

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The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
David Wu 2017-09-20 14:28:18 +08:00 committed by Philipp Tomsich
parent ae3ed042ed
commit 2e4ce50d1a
3 changed files with 39 additions and 1 deletions
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5
arch/arm/include/asm/arch-rockchip/cru_rv1108.h
View File

@ -90,6 +90,11 @@ enum {
CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_SHIFT = 0,
CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
/* CLKSEL_CON22 */
CLK_SARADC_DIV_CON_SHIFT= 0,
CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
CLK_SARADC_DIV_CON_WIDTH= 10,
/* CLKSEL24_CON */ /* CLKSEL24_CON */
MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_SHIFT = 12,
MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,

33
drivers/clk/rockchip/clk_rv1108.c
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@ -5,6 +5,7 @@
*/ */
#include <common.h> #include <common.h>
#include <bitfield.h>
#include <clk-uclass.h> #include <clk-uclass.h>
#include <dm.h> #include <dm.h>
#include <errno.h> #include <errno.h>
@ -36,7 +37,7 @@ enum {
#hz "Hz cannot be hit with PLL "\ #hz "Hz cannot be hit with PLL "\
"divisors on line " __stringify(__LINE__)); "divisors on line " __stringify(__LINE__));
/* use interge mode*/ /* use integer mode */
static inline int rv1108_pll_id(enum rk_clk_id clk_id) static inline int rv1108_pll_id(enum rk_clk_id clk_id)
{ {
int id = 0; int id = 0;
@ -130,6 +131,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
return DIV_TO_RATE(pll_rate, div); return DIV_TO_RATE(pll_rate, div);
} }
static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
{
u32 div, val;
val = readl(&cru->clksel_con[22]);
div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
CLK_SARADC_DIV_CON_WIDTH);
return DIV_TO_RATE(OSC_HZ, div);
}
static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
{
int src_clk_div;
src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
assert(src_clk_div < 128);
rk_clrsetreg(&cru->clksel_con[22],
CLK_SARADC_DIV_CON_MASK,
src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
return rv1108_saradc_get_clk(cru);
}
static ulong rv1108_clk_get_rate(struct clk *clk) static ulong rv1108_clk_get_rate(struct clk *clk)
{ {
struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
@ -137,6 +163,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
switch (clk->id) { switch (clk->id) {
case 0 ... 63: case 0 ... 63:
return rkclk_pll_get_rate(priv->cru, clk->id); return rkclk_pll_get_rate(priv->cru, clk->id);
case SCLK_SARADC:
return rv1108_saradc_get_clk(priv->cru);
default: default:
return -ENOENT; return -ENOENT;
} }
@ -154,6 +182,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SFC: case SCLK_SFC:
new_rate = rv1108_sfc_set_clk(priv->cru, rate); new_rate = rv1108_sfc_set_clk(priv->cru, rate);
break; break;
case SCLK_SARADC:
new_rate = rv1108_saradc_set_clk(priv->cru, rate);
break;
default: default:
return -ENOENT; return -ENOENT;
} }

2
include/dt-bindings/clock/rv1108-cru.h
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@ -39,6 +39,7 @@
#define SCLK_MAC_TX 88 #define SCLK_MAC_TX 88
#define SCLK_MACREF 89 #define SCLK_MACREF 89
#define SCLK_MACREF_OUT 90 #define SCLK_MACREF_OUT 90
#define SCLK_SARADC 91
/* aclk gates */ /* aclk gates */
@ -67,6 +68,7 @@
#define PCLK_TIMER 270 #define PCLK_TIMER 270
#define PCLK_PERI 271 #define PCLK_PERI 271
#define PCLK_GMAC 272 #define PCLK_GMAC 272
#define PCLK_SARADC 273
/* hclk gates */ /* hclk gates */
#define HCLK_I2S0_8CH 320 #define HCLK_I2S0_8CH 320