mirror of
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- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAmKsehgACgkQ4rK92eCq k3UexAf+JThCd7FlN3OkTVKIdZKeNm2KpQxrqt20whiqp/nSUzxXrjdlCTKZEER2 lLJoVnwr+bkmdlqsa6gAZXSsd0lUv37XnLsLA5or278tFNlKp6gzYrz49FR59mVC ie7/NlY5FgM5qmKGCob7tjwJ78r2/S3T2EaLiAMWUmw2UB5KZU6h3napHZ+1T0se vaEAVRzAaZeYzKU3k6RBSv2tXQ6ssvfpp9RcXpRGtrN908AqDhHiOfntuOrnsEe0 9rjY1DSXO9a5WqHRm2KQ3FrA/By2layQ+4WH/HgIPHasisnmo3E/euVWmhtTaiT/ g5bOLwyFQ2/RvdMlMxXlKUcuMfNwRA== =Hhzj -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next - Add STM32MP13 SoCs support with associated board STM32M135F-DK - Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards
This commit is contained in:
Tom Rini
commit
2f7821a927
@ -496,7 +496,7 @@ S: Maintained
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|||||||
F: arch/arm/mach-stm32mp/
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F: arch/arm/mach-stm32mp/
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F: doc/board/st/
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F: doc/board/st/
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F: drivers/adc/stm32-adc*
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F: drivers/adc/stm32-adc*
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F: drivers/clk/clk_stm32mp1.c
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F: drivers/clk/stm32/
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F: drivers/gpio/stm32_gpio.c
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F: drivers/gpio/stm32_gpio.c
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F: drivers/hwspinlock/stm32_hwspinlock.c
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F: drivers/hwspinlock/stm32_hwspinlock.c
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F: drivers/i2c/stm32f7_i2c.c
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F: drivers/i2c/stm32f7_i2c.c
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@ -1928,7 +1928,7 @@ config ARCH_STM32
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imply CMD_DM
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imply CMD_DM
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config ARCH_STI
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config ARCH_STI
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bool "Support STMicrolectronics SoCs"
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bool "Support STMicroelectronics SoCs"
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select BLK
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select BLK
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select CPU_V7A
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select CPU_V7A
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select DM
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select DM
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@ -1956,7 +1956,6 @@ config ARCH_STM32MP
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select OF_SYSTEM_SETUP
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select OF_SYSTEM_SETUP
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select PINCTRL
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select PINCTRL
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select REGMAP
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select REGMAP
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select SUPPORT_SPL
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select SYSCON
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select SYSCON
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select SYSRESET
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select SYSRESET
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select SYS_THUMB_BUILD
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select SYS_THUMB_BUILD
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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/*
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* (C) Copyright 2014 stmicroelectronics
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* (C) Copyright 2014 STMicroelectronics
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*/
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*/
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#include <config.h>
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#include <config.h>
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@ -1162,6 +1162,9 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
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dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
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dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
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dtb-$(CONFIG_STM32MP13x) += \
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stm32mp135f-dk.dtb
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dtb-$(CONFIG_STM32MP15x) += \
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dtb-$(CONFIG_STM32MP15x) += \
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stm32mp157a-dk1.dtb \
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stm32mp157a-dk1.dtb \
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stm32mp157a-icore-stm32mp1-ctouch2.dtb \
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stm32mp157a-icore-stm32mp1-ctouch2.dtb \
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123
arch/arm/dts/stm32mp13-pinctrl.dtsi
Normal file
123
arch/arm/dts/stm32mp13-pinctrl.dtsi
Normal file
@ -0,0 +1,123 @@
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|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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sdmmc1_b4_pins_a: sdmmc1-b4-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <1>;
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drive-open-drain;
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bias-disable;
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};
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};
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sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
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<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
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};
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};
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sdmmc1_clk_pins_a: sdmmc1-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2 {
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pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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slew-rate = <1>;
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drive-open-drain;
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bias-pull-up;
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};
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};
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sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
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<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
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<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
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};
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};
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sdmmc2_clk_pins_a: sdmmc2-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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uart4_pins_a: uart4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
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bias-disable;
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};
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};
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};
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91
arch/arm/dts/stm32mp13-u-boot.dtsi
Normal file
91
arch/arm/dts/stm32mp13-u-boot.dtsi
Normal file
@ -0,0 +1,91 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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||||||
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
|
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|
gpio6 = &gpiog;
|
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|
gpio7 = &gpioh;
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|
gpio8 = &gpioi;
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pinctrl0 = &pinctrl;
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|
};
|
||||||
|
|
||||||
|
/* need PSCI for sysreset during board_f */
|
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|
psci {
|
||||||
|
u-boot,dm-pre-proper;
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||||||
|
};
|
||||||
|
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||||||
|
soc {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
|
||||||
|
ddr: ddr@5a003000 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
|
||||||
|
compatible = "st,stm32mp13-ddr";
|
||||||
|
|
||||||
|
reg = <0x5A003000 0x550
|
||||||
|
0x5A004000 0x234>;
|
||||||
|
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&bsec {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioa {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpiob {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioc {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpiod {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioe {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpiof {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpiog {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioh {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpioi {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pinctrl {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&syscfg {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
358
arch/arm/dts/stm32mp131.dtsi
Normal file
358
arch/arm/dts/stm32mp131.dtsi
Normal file
@ -0,0 +1,358 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu0: cpu@0 {
|
||||||
|
compatible = "arm,cortex-a7";
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
arm-pmu {
|
||||||
|
compatible = "arm,cortex-a7-pmu";
|
||||||
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-affinity = <&cpu0>;
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clocks {
|
||||||
|
clk_axi: clk-axi {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <266500000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_hse: clk-hse {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <24000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_hsi: clk-hsi {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <64000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_lsi: clk-lsi {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <32000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_pclk3: clk-pclk3 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <104438965>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_pclk4: clk-pclk4 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <133250000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_pll4_p: clk-pll4_p {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_pll4_r: clk-pll4_r {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <99000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
intc: interrupt-controller@a0021000 {
|
||||||
|
compatible = "arm,cortex-a7-gic";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0xa0021000 0x1000>,
|
||||||
|
<0xa0022000 0x2000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
psci {
|
||||||
|
compatible = "arm,psci-1.0";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv7-timer";
|
||||||
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
always-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
uart4: serial@40010000 {
|
||||||
|
compatible = "st,stm32h7-uart";
|
||||||
|
reg = <0x40010000 0x400>;
|
||||||
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_hsi>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
dma1: dma-controller@48000000 {
|
||||||
|
compatible = "st,stm32-dma";
|
||||||
|
reg = <0x48000000 0x400>;
|
||||||
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
#dma-cells = <4>;
|
||||||
|
st,mem2mem;
|
||||||
|
dma-requests = <8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma2: dma-controller@48001000 {
|
||||||
|
compatible = "st,stm32-dma";
|
||||||
|
reg = <0x48001000 0x400>;
|
||||||
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
#dma-cells = <4>;
|
||||||
|
st,mem2mem;
|
||||||
|
dma-requests = <8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dmamux1: dma-router@48002000 {
|
||||||
|
compatible = "st,stm32h7-dmamux";
|
||||||
|
reg = <0x48002000 0x40>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
#dma-cells = <3>;
|
||||||
|
dma-masters = <&dma1 &dma2>;
|
||||||
|
dma-requests = <128>;
|
||||||
|
dma-channels = <16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
exti: interrupt-controller@5000d000 {
|
||||||
|
compatible = "st,stm32mp13-exti", "syscon";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x5000d000 0x400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
syscfg: syscon@50020000 {
|
||||||
|
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||||
|
reg = <0x50020000 0x400>;
|
||||||
|
clocks = <&clk_pclk3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdma: dma-controller@58000000 {
|
||||||
|
compatible = "st,stm32h7-mdma";
|
||||||
|
reg = <0x58000000 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
#dma-cells = <5>;
|
||||||
|
dma-channels = <32>;
|
||||||
|
dma-requests = <48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sdmmc1: mmc@58005000 {
|
||||||
|
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||||||
|
arm,primecell-periphid = <0x20253180>;
|
||||||
|
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "cmd_irq";
|
||||||
|
clocks = <&clk_pll4_p>;
|
||||||
|
clock-names = "apb_pclk";
|
||||||
|
cap-sd-highspeed;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
max-frequency = <130000000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
sdmmc2: mmc@58007000 {
|
||||||
|
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||||||
|
arm,primecell-periphid = <0x20253180>;
|
||||||
|
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "cmd_irq";
|
||||||
|
clocks = <&clk_pll4_p>;
|
||||||
|
clock-names = "apb_pclk";
|
||||||
|
cap-sd-highspeed;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
max-frequency = <130000000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
iwdg2: watchdog@5a002000 {
|
||||||
|
compatible = "st,stm32mp1-iwdg";
|
||||||
|
reg = <0x5a002000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>, <&clk_lsi>;
|
||||||
|
clock-names = "pclk", "lsi";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
bsec: efuse@5c005000 {
|
||||||
|
compatible = "st,stm32mp13-bsec";
|
||||||
|
reg = <0x5c005000 0x400>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
part_number_otp: part_number_otp@4 {
|
||||||
|
reg = <0x4 0x2>;
|
||||||
|
};
|
||||||
|
ts_cal1: calib@5c {
|
||||||
|
reg = <0x5c 0x2>;
|
||||||
|
};
|
||||||
|
ts_cal2: calib@5e {
|
||||||
|
reg = <0x5e 0x2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Break node order to solve dependency probe issue between
|
||||||
|
* pinctrl and exti.
|
||||||
|
*/
|
||||||
|
pinctrl: pin-controller@50002000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "st,stm32mp135-pinctrl";
|
||||||
|
ranges = <0 0x50002000 0x8400>;
|
||||||
|
pins-are-numbered;
|
||||||
|
|
||||||
|
gpioa: gpio@50002000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x0 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOA";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 0 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiob: gpio@50003000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x1000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOB";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 16 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioc: gpio@50004000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x2000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOC";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 32 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiod: gpio@50005000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x3000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOD";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 48 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioe: gpio@50006000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x4000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOE";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 64 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiof: gpio@50007000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x5000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOF";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 80 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpiog: gpio@50008000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x6000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOG";
|
||||||
|
ngpios = <16>;
|
||||||
|
gpio-ranges = <&pinctrl 0 96 16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioh: gpio@50009000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x7000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOH";
|
||||||
|
ngpios = <15>;
|
||||||
|
gpio-ranges = <&pinctrl 0 112 15>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpioi: gpio@5000a000 {
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
reg = <0x8000 0x400>;
|
||||||
|
clocks = <&clk_pclk4>;
|
||||||
|
st,bank-name = "GPIOI";
|
||||||
|
ngpios = <8>;
|
||||||
|
gpio-ranges = <&pinctrl 0 128 8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
37
arch/arm/dts/stm32mp133.dtsi
Normal file
37
arch/arm/dts/stm32mp133.dtsi
Normal file
@ -0,0 +1,37 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "stm32mp131.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
soc {
|
||||||
|
m_can1: can@4400e000 {
|
||||||
|
compatible = "bosch,m_can";
|
||||||
|
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
||||||
|
reg-names = "m_can", "message_ram";
|
||||||
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "int0", "int1";
|
||||||
|
clocks = <&clk_hse>, <&clk_pll4_r>;
|
||||||
|
clock-names = "hclk", "cclk";
|
||||||
|
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
m_can2: can@4400f000 {
|
||||||
|
compatible = "bosch,m_can";
|
||||||
|
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||||
|
reg-names = "m_can", "message_ram";
|
||||||
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "int0", "int1";
|
||||||
|
clocks = <&clk_hse>, <&clk_pll4_r>;
|
||||||
|
clock-names = "hclk", "cclk";
|
||||||
|
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
12
arch/arm/dts/stm32mp135.dtsi
Normal file
12
arch/arm/dts/stm32mp135.dtsi
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "stm32mp133.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
soc {
|
||||||
|
};
|
||||||
|
};
|
||||||
30
arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
Normal file
30
arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
Normal file
@ -0,0 +1,30 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "stm32mp13-u-boot.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
aliases {
|
||||||
|
mmc0 = &sdmmc1;
|
||||||
|
};
|
||||||
|
|
||||||
|
config {
|
||||||
|
u-boot,mmc-env-partition = "u-boot-env";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4_pins_a {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
pins1 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
pins2 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
};
|
||||||
57
arch/arm/dts/stm32mp135f-dk.dts
Normal file
57
arch/arm/dts/stm32mp135f-dk.dts
Normal file
@ -0,0 +1,57 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "stm32mp135.dtsi"
|
||||||
|
#include "stm32mp13xf.dtsi"
|
||||||
|
#include "stm32mp13-pinctrl.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
|
||||||
|
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart4;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@c0000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0xc0000000 0x20000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vdd_sd: vdd-sd {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "vdd_sd";
|
||||||
|
regulator-min-microvolt = <2900000>;
|
||||||
|
regulator-max-microvolt = <2900000>;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&iwdg2 {
|
||||||
|
timeout-sec = <32>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc1 {
|
||||||
|
pinctrl-names = "default", "opendrain", "sleep";
|
||||||
|
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
|
||||||
|
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
|
||||||
|
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||||
|
broken-cd;
|
||||||
|
disable-wp;
|
||||||
|
st,neg-edge;
|
||||||
|
bus-width = <4>;
|
||||||
|
vmmc-supply = <&vdd_sd>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart4 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart4_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
17
arch/arm/dts/stm32mp13xc.dtsi
Normal file
17
arch/arm/dts/stm32mp13xc.dtsi
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/ {
|
||||||
|
soc {
|
||||||
|
cryp: crypto@54002000 {
|
||||||
|
compatible = "st,stm32mp1-cryp";
|
||||||
|
reg = <0x54002000 0x400>;
|
||||||
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_axi>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
17
arch/arm/dts/stm32mp13xf.dtsi
Normal file
17
arch/arm/dts/stm32mp13xf.dtsi
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||||
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/ {
|
||||||
|
soc {
|
||||||
|
cryp: crypto@54002000 {
|
||||||
|
compatible = "st,stm32mp1-cryp";
|
||||||
|
reg = <0x54002000 0x400>;
|
||||||
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clk_axi>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@ -9,7 +9,7 @@ choice
|
|||||||
config TARGET_STIH410_B2260
|
config TARGET_STIH410_B2260
|
||||||
bool "96Boards STiH410-B2260"
|
bool "96Boards STiH410-B2260"
|
||||||
help
|
help
|
||||||
Support for 96Board STiH410-B2260 based on STMicrolectronics
|
Support for 96Board STiH410-B2260 based on STMicroelectronics
|
||||||
STiH410 soc. This board complies with 96Board Open Platform
|
STiH410 soc. This board complies with 96Board Open Platform
|
||||||
Specifications. Features:
|
Specifications. Features:
|
||||||
- 1GB DDR
|
- 1GB DDR
|
||||||
|
|||||||
@ -33,6 +33,28 @@ config SYS_MALLOC_LEN
|
|||||||
config ENV_SIZE
|
config ENV_SIZE
|
||||||
default 0x2000
|
default 0x2000
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "Select STMicroelectronics STM32MPxxx Soc"
|
||||||
|
default STM32MP15x
|
||||||
|
|
||||||
|
config STM32MP13x
|
||||||
|
bool "Support STMicroelectronics STM32MP13x Soc"
|
||||||
|
select ARM_SMCCC
|
||||||
|
select CPU_V7A
|
||||||
|
select CPU_V7_HAS_NONSEC
|
||||||
|
select CPU_V7_HAS_VIRT
|
||||||
|
select OF_BOARD
|
||||||
|
select OF_BOARD_SETUP
|
||||||
|
select PINCTRL_STM32
|
||||||
|
select STM32_RCC
|
||||||
|
select STM32_RESET
|
||||||
|
select STM32_SERIAL
|
||||||
|
select SYS_ARCH_TIMER
|
||||||
|
imply CMD_NVEDIT_INFO
|
||||||
|
help
|
||||||
|
support of STMicroelectronics SOC STM32MP13x family
|
||||||
|
STMicroelectronics MPU with core ARMv7
|
||||||
|
|
||||||
config STM32MP15x
|
config STM32MP15x
|
||||||
bool "Support STMicroelectronics STM32MP15x Soc"
|
bool "Support STMicroelectronics STM32MP15x Soc"
|
||||||
select ARCH_SUPPORT_PSCI
|
select ARCH_SUPPORT_PSCI
|
||||||
@ -46,6 +68,7 @@ config STM32MP15x
|
|||||||
select STM32_RCC
|
select STM32_RCC
|
||||||
select STM32_RESET
|
select STM32_RESET
|
||||||
select STM32_SERIAL
|
select STM32_SERIAL
|
||||||
|
select SUPPORT_SPL
|
||||||
select SYS_ARCH_TIMER
|
select SYS_ARCH_TIMER
|
||||||
imply CMD_NVEDIT_INFO
|
imply CMD_NVEDIT_INFO
|
||||||
help
|
help
|
||||||
@ -53,92 +76,8 @@ config STM32MP15x
|
|||||||
STM32MP157, STM32MP153 or STM32MP151
|
STM32MP157, STM32MP153 or STM32MP151
|
||||||
STMicroelectronics MPU with core ARMv7
|
STMicroelectronics MPU with core ARMv7
|
||||||
dual core A7 for STM32MP157/3, monocore for STM32MP151
|
dual core A7 for STM32MP157/3, monocore for STM32MP151
|
||||||
target all the STMicroelectronics board with SOC STM32MP1 family
|
|
||||||
|
|
||||||
config STM32MP15x_STM32IMAGE
|
|
||||||
bool "Support STM32 image for generated U-Boot image"
|
|
||||||
depends on STM32MP15x && TFABOOT
|
|
||||||
help
|
|
||||||
Support of STM32 image generation for SOC STM32MP15x
|
|
||||||
for TF-A boot when FIP container is not used
|
|
||||||
|
|
||||||
choice
|
|
||||||
prompt "STM32MP15x board select"
|
|
||||||
optional
|
|
||||||
|
|
||||||
config TARGET_ST_STM32MP15x
|
|
||||||
bool "STMicroelectronics STM32MP15x boards"
|
|
||||||
select STM32MP15x
|
|
||||||
imply BOOTSTAGE
|
|
||||||
imply CMD_BOOTSTAGE
|
|
||||||
imply CMD_CLS if CMD_BMP
|
|
||||||
imply DISABLE_CONSOLE
|
|
||||||
imply PRE_CONSOLE_BUFFER
|
|
||||||
imply SILENT_CONSOLE
|
|
||||||
help
|
|
||||||
target the STMicroelectronics board with SOC STM32MP15x
|
|
||||||
managed by board/st/stm32mp1:
|
|
||||||
Evalulation board (EV1) or Discovery board (DK1 and DK2).
|
|
||||||
The difference between board are managed with devicetree
|
|
||||||
|
|
||||||
config TARGET_MICROGEA_STM32MP1
|
|
||||||
bool "Engicam MicroGEA STM32MP1 SOM"
|
|
||||||
select STM32MP15x
|
|
||||||
imply BOOTSTAGE
|
|
||||||
imply CMD_BOOTSTAGE
|
|
||||||
imply CMD_CLS if CMD_BMP
|
|
||||||
imply DISABLE_CONSOLE
|
|
||||||
imply PRE_CONSOLE_BUFFER
|
|
||||||
imply SILENT_CONSOLE
|
|
||||||
help
|
|
||||||
MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
|
|
||||||
|
|
||||||
MicroGEA STM32MP1 MicroDev 2.0:
|
|
||||||
* MicroDev 2.0 is a general purpose miniature carrier board with CAN,
|
|
||||||
LTE and LVDS panel interfaces.
|
|
||||||
* MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
|
|
||||||
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
|
|
||||||
|
|
||||||
MicroGEA STM32MP1 MicroDev 2.0 7" OF:
|
|
||||||
* 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
|
|
||||||
panel and toucscreen.
|
|
||||||
* MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
|
|
||||||
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
|
|
||||||
Open Frame Solution board.
|
|
||||||
|
|
||||||
config TARGET_ICORE_STM32MP1
|
|
||||||
bool "Engicam i.Core STM32MP1 SOM"
|
|
||||||
select STM32MP15x
|
|
||||||
imply BOOTSTAGE
|
|
||||||
imply CMD_BOOTSTAGE
|
|
||||||
imply CMD_CLS if CMD_BMP
|
|
||||||
imply DISABLE_CONSOLE
|
|
||||||
imply PRE_CONSOLE_BUFFER
|
|
||||||
imply SILENT_CONSOLE
|
|
||||||
help
|
|
||||||
i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
|
|
||||||
|
|
||||||
i.Core STM32MP1 EDIMM2.2:
|
|
||||||
* EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
|
|
||||||
* i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
|
|
||||||
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
|
|
||||||
|
|
||||||
i.Core STM32MP1 C.TOUCH 2.0
|
|
||||||
* C.TOUCH 2.0 is a general purpose Carrier board.
|
|
||||||
* i.Core STM32MP1 needs to mount on top of this Carrier board
|
|
||||||
for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
|
|
||||||
|
|
||||||
config TARGET_DH_STM32MP1_PDK2
|
|
||||||
bool "DH STM32MP1 PDK2"
|
|
||||||
select STM32MP15x
|
|
||||||
help
|
|
||||||
Target the DH PDK2 development kit with STM32MP15x SoM.
|
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
config SYS_TEXT_BASE
|
|
||||||
default 0xC0100000
|
|
||||||
|
|
||||||
config NR_DRAM_BANKS
|
config NR_DRAM_BANKS
|
||||||
default 1
|
default 1
|
||||||
|
|
||||||
@ -164,7 +103,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
|
|||||||
|
|
||||||
config STM32_ETZPC
|
config STM32_ETZPC
|
||||||
bool "STM32 Extended TrustZone Protection"
|
bool "STM32 Extended TrustZone Protection"
|
||||||
depends on STM32MP15x
|
depends on STM32MP15x || STM32MP13x
|
||||||
default y
|
default y
|
||||||
imply BOOTP_SERVERIP
|
imply BOOTP_SERVERIP
|
||||||
help
|
help
|
||||||
@ -187,41 +126,8 @@ config CMD_STM32KEY
|
|||||||
This command is used to evaluate the secure boot on stm32mp SOC,
|
This command is used to evaluate the secure boot on stm32mp SOC,
|
||||||
it is deactivated by default in real products.
|
it is deactivated by default in real products.
|
||||||
|
|
||||||
config PRE_CON_BUF_ADDR
|
source "arch/arm/mach-stm32mp/Kconfig.13x"
|
||||||
default 0xC02FF000
|
source "arch/arm/mach-stm32mp/Kconfig.15x"
|
||||||
|
|
||||||
config PRE_CON_BUF_SZ
|
|
||||||
default 4096
|
|
||||||
|
|
||||||
config BOOTSTAGE_STASH_ADDR
|
|
||||||
default 0xC3000000
|
|
||||||
|
|
||||||
if BOOTCOUNT_GENERIC
|
|
||||||
config SYS_BOOTCOUNT_SINGLEWORD
|
|
||||||
default y
|
|
||||||
|
|
||||||
# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
|
|
||||||
config SYS_BOOTCOUNT_ADDR
|
|
||||||
default 0x5C00A154
|
|
||||||
endif
|
|
||||||
|
|
||||||
if DEBUG_UART
|
|
||||||
|
|
||||||
config DEBUG_UART_BOARD_INIT
|
|
||||||
default y
|
|
||||||
|
|
||||||
# debug on UART4 by default
|
|
||||||
config DEBUG_UART_BASE
|
|
||||||
default 0x40010000
|
|
||||||
|
|
||||||
# clock source is HSI on reset
|
|
||||||
config DEBUG_UART_CLOCK
|
|
||||||
default 64000000
|
|
||||||
endif
|
|
||||||
|
|
||||||
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
|
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
|
||||||
source "board/dhelectronics/dh_stm32mp1/Kconfig"
|
|
||||||
source "board/engicam/stm32mp1/Kconfig"
|
|
||||||
source "board/st/stm32mp1/Kconfig"
|
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|||||||
57
arch/arm/mach-stm32mp/Kconfig.13x
Normal file
57
arch/arm/mach-stm32mp/Kconfig.13x
Normal file
@ -0,0 +1,57 @@
|
|||||||
|
if STM32MP13x
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "STM32MP13x board select"
|
||||||
|
optional
|
||||||
|
|
||||||
|
config TARGET_ST_STM32MP13x
|
||||||
|
bool "STMicroelectronics STM32MP13x boards"
|
||||||
|
imply BOOTSTAGE
|
||||||
|
imply CMD_BOOTSTAGE
|
||||||
|
imply CMD_CLS if CMD_BMP
|
||||||
|
imply DISABLE_CONSOLE
|
||||||
|
imply PRE_CONSOLE_BUFFER
|
||||||
|
imply SILENT_CONSOLE
|
||||||
|
help
|
||||||
|
target the STMicroelectronics board with SOC STM32MP13x
|
||||||
|
managed by board/st/stm32mp1.
|
||||||
|
The difference between board are managed with devicetree
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
config SYS_TEXT_BASE
|
||||||
|
default 0xC0000000
|
||||||
|
|
||||||
|
config PRE_CON_BUF_ADDR
|
||||||
|
default 0xC0800000
|
||||||
|
|
||||||
|
config PRE_CON_BUF_SZ
|
||||||
|
default 4096
|
||||||
|
|
||||||
|
config BOOTSTAGE_STASH_ADDR
|
||||||
|
default 0xC3000000
|
||||||
|
|
||||||
|
if BOOTCOUNT_GENERIC
|
||||||
|
config SYS_BOOTCOUNT_SINGLEWORD
|
||||||
|
default y
|
||||||
|
|
||||||
|
# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(31)
|
||||||
|
config SYS_BOOTCOUNT_ADDR
|
||||||
|
default 0x5C00A17C
|
||||||
|
endif
|
||||||
|
|
||||||
|
if DEBUG_UART
|
||||||
|
|
||||||
|
# debug on UART4 by default
|
||||||
|
config DEBUG_UART_BASE
|
||||||
|
default 0x40010000
|
||||||
|
|
||||||
|
# clock source is HSI on reset
|
||||||
|
config DEBUG_UART_CLOCK
|
||||||
|
default 48000000 if STM32_FPGA
|
||||||
|
default 64000000
|
||||||
|
endif
|
||||||
|
|
||||||
|
source "board/st/stm32mp1/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
135
arch/arm/mach-stm32mp/Kconfig.15x
Normal file
135
arch/arm/mach-stm32mp/Kconfig.15x
Normal file
@ -0,0 +1,135 @@
|
|||||||
|
if STM32MP15x
|
||||||
|
|
||||||
|
config STM32MP15x_STM32IMAGE
|
||||||
|
bool "Support STM32 image for generated U-Boot image"
|
||||||
|
depends on TFABOOT
|
||||||
|
help
|
||||||
|
Support of STM32 image generation for SOC STM32MP15x
|
||||||
|
for TF-A boot when FIP container is not used
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "STM32MP15x board select"
|
||||||
|
optional
|
||||||
|
|
||||||
|
config TARGET_ST_STM32MP15x
|
||||||
|
bool "STMicroelectronics STM32MP15x boards"
|
||||||
|
imply BOOTSTAGE
|
||||||
|
imply CMD_BOOTSTAGE
|
||||||
|
imply CMD_CLS if CMD_BMP
|
||||||
|
imply DISABLE_CONSOLE
|
||||||
|
imply PRE_CONSOLE_BUFFER
|
||||||
|
imply SILENT_CONSOLE
|
||||||
|
help
|
||||||
|
target the STMicroelectronics board with SOC STM32MP15x
|
||||||
|
managed by board/st/stm32mp1:
|
||||||
|
Evalulation board (EV1) or Discovery board (DK1 and DK2).
|
||||||
|
The difference between board are managed with devicetree
|
||||||
|
|
||||||
|
config TARGET_DH_STM32MP1_PDK2
|
||||||
|
bool "DH STM32MP1 PDK2"
|
||||||
|
help
|
||||||
|
Target the DH PDK2 development kit with STM32MP15x SoM.
|
||||||
|
|
||||||
|
config TARGET_MICROGEA_STM32MP1
|
||||||
|
bool "Engicam MicroGEA STM32MP1 SOM"
|
||||||
|
imply BOOTSTAGE
|
||||||
|
imply CMD_BOOTSTAGE
|
||||||
|
imply CMD_CLS if CMD_BMP
|
||||||
|
imply DISABLE_CONSOLE
|
||||||
|
imply PRE_CONSOLE_BUFFER
|
||||||
|
imply SILENT_CONSOLE
|
||||||
|
help
|
||||||
|
MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
|
||||||
|
|
||||||
|
MicroGEA STM32MP1 MicroDev 2.0:
|
||||||
|
* MicroDev 2.0 is a general purpose miniature carrier board with CAN,
|
||||||
|
LTE and LVDS panel interfaces.
|
||||||
|
* MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
|
||||||
|
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
|
||||||
|
|
||||||
|
MicroGEA STM32MP1 MicroDev 2.0 7" OF:
|
||||||
|
* 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
|
||||||
|
panel and toucscreen.
|
||||||
|
* MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
|
||||||
|
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
|
||||||
|
Open Frame Solution board.
|
||||||
|
|
||||||
|
config TARGET_ICORE_STM32MP1
|
||||||
|
bool "Engicam i.Core STM32MP1 SOM"
|
||||||
|
imply BOOTSTAGE
|
||||||
|
imply CMD_BOOTSTAGE
|
||||||
|
imply CMD_CLS if CMD_BMP
|
||||||
|
imply DISABLE_CONSOLE
|
||||||
|
imply PRE_CONSOLE_BUFFER
|
||||||
|
imply SILENT_CONSOLE
|
||||||
|
help
|
||||||
|
i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
|
||||||
|
|
||||||
|
i.Core STM32MP1 EDIMM2.2:
|
||||||
|
* EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
|
||||||
|
* i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
|
||||||
|
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
|
||||||
|
|
||||||
|
i.Core STM32MP1 C.TOUCH 2.0
|
||||||
|
* C.TOUCH 2.0 is a general purpose Carrier board.
|
||||||
|
* i.Core STM32MP1 needs to mount on top of this Carrier board
|
||||||
|
for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
config STM32MP15_PWR
|
||||||
|
bool "Enable driver for STM32MP15x PWR"
|
||||||
|
depends on DM_REGULATOR && DM_PMIC
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This config enables implementation of driver-model pmic and
|
||||||
|
regulator uclass features for access to STM32MP15x PWR.
|
||||||
|
|
||||||
|
config SPL_STM32MP15_PWR
|
||||||
|
bool "Enable driver for STM32MP15x PWR in SPL"
|
||||||
|
depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This config enables implementation of driver-model pmic and
|
||||||
|
regulator uclass features for access to STM32MP15x PWR in SPL.
|
||||||
|
|
||||||
|
config SYS_TEXT_BASE
|
||||||
|
default 0xC0100000
|
||||||
|
|
||||||
|
config PRE_CON_BUF_ADDR
|
||||||
|
default 0xC02FF000
|
||||||
|
|
||||||
|
config PRE_CON_BUF_SZ
|
||||||
|
default 4096
|
||||||
|
|
||||||
|
config BOOTSTAGE_STASH_ADDR
|
||||||
|
default 0xC3000000
|
||||||
|
|
||||||
|
if BOOTCOUNT_GENERIC
|
||||||
|
config SYS_BOOTCOUNT_SINGLEWORD
|
||||||
|
default y
|
||||||
|
|
||||||
|
# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
|
||||||
|
config SYS_BOOTCOUNT_ADDR
|
||||||
|
default 0x5C00A154
|
||||||
|
endif
|
||||||
|
|
||||||
|
if DEBUG_UART
|
||||||
|
|
||||||
|
config DEBUG_UART_BOARD_INIT
|
||||||
|
default y
|
||||||
|
|
||||||
|
# debug on UART4 by default
|
||||||
|
config DEBUG_UART_BASE
|
||||||
|
default 0x40010000
|
||||||
|
|
||||||
|
# clock source is HSI on reset
|
||||||
|
config DEBUG_UART_CLOCK
|
||||||
|
default 64000000
|
||||||
|
endif
|
||||||
|
|
||||||
|
source "board/st/stm32mp1/Kconfig"
|
||||||
|
source "board/dhelectronics/dh_stm32mp1/Kconfig"
|
||||||
|
source "board/engicam/stm32mp1/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
@ -8,6 +8,9 @@ obj-y += dram_init.o
|
|||||||
obj-y += syscon.o
|
obj-y += syscon.o
|
||||||
obj-y += bsec.o
|
obj-y += bsec.o
|
||||||
|
|
||||||
|
obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
|
||||||
|
obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
|
||||||
|
|
||||||
ifdef CONFIG_SPL_BUILD
|
ifdef CONFIG_SPL_BUILD
|
||||||
obj-y += spl.o
|
obj-y += spl.o
|
||||||
obj-y += tzc400.o
|
obj-y += tzc400.o
|
||||||
@ -19,5 +22,5 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o
|
|||||||
obj-$(CONFIG_TFABOOT) += boot_params.o
|
obj-$(CONFIG_TFABOOT) += boot_params.o
|
||||||
endif
|
endif
|
||||||
|
|
||||||
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
|
obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
|
||||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||||
|
|||||||
@ -632,3 +632,20 @@ bool bsec_dbgswenable(void)
|
|||||||
|
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
u32 get_otp(int index, int shift, int mask)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
struct udevice *dev;
|
||||||
|
u32 otp = 0;
|
||||||
|
|
||||||
|
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||||
|
DM_DRIVER_GET(stm32mp_bsec),
|
||||||
|
&dev);
|
||||||
|
|
||||||
|
if (!ret)
|
||||||
|
ret = misc_read(dev, STM32_BSEC_SHADOW(index),
|
||||||
|
&otp, sizeof(otp));
|
||||||
|
|
||||||
|
return (otp >> shift) & mask;
|
||||||
|
}
|
||||||
|
|||||||
@ -16,7 +16,6 @@
|
|||||||
#include <misc.h>
|
#include <misc.h>
|
||||||
#include <net.h>
|
#include <net.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch/bsec.h>
|
|
||||||
#include <asm/arch/stm32.h>
|
#include <asm/arch/stm32.h>
|
||||||
#include <asm/arch/sys_proto.h>
|
#include <asm/arch/sys_proto.h>
|
||||||
#include <asm/global_data.h>
|
#include <asm/global_data.h>
|
||||||
@ -24,67 +23,6 @@
|
|||||||
#include <dm/uclass.h>
|
#include <dm/uclass.h>
|
||||||
#include <linux/bitops.h>
|
#include <linux/bitops.h>
|
||||||
|
|
||||||
/* RCC register */
|
|
||||||
#define RCC_TZCR (STM32_RCC_BASE + 0x00)
|
|
||||||
#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
|
|
||||||
#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
|
|
||||||
#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
|
|
||||||
#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
|
|
||||||
#define RCC_BDCR_VSWRST BIT(31)
|
|
||||||
#define RCC_BDCR_RTCSRC GENMASK(17, 16)
|
|
||||||
#define RCC_DBGCFGR_DBGCKEN BIT(8)
|
|
||||||
|
|
||||||
/* Security register */
|
|
||||||
#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
|
|
||||||
#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
|
|
||||||
|
|
||||||
#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
|
|
||||||
#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
|
|
||||||
#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
|
|
||||||
|
|
||||||
#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
|
|
||||||
|
|
||||||
#define PWR_CR1 (STM32_PWR_BASE + 0x00)
|
|
||||||
#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
|
|
||||||
#define PWR_CR1_DBP BIT(8)
|
|
||||||
#define PWR_MCUCR_SBF BIT(6)
|
|
||||||
|
|
||||||
/* DBGMCU register */
|
|
||||||
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
|
|
||||||
#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
|
|
||||||
#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
|
|
||||||
#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
|
|
||||||
#define DBGMCU_IDC_DEV_ID_SHIFT 0
|
|
||||||
#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
|
|
||||||
#define DBGMCU_IDC_REV_ID_SHIFT 16
|
|
||||||
|
|
||||||
/* GPIOZ registers */
|
|
||||||
#define GPIOZ_SECCFGR 0x54004030
|
|
||||||
|
|
||||||
/* boot interface from Bootrom
|
|
||||||
* - boot instance = bit 31:16
|
|
||||||
* - boot device = bit 15:0
|
|
||||||
*/
|
|
||||||
#define BOOTROM_PARAM_ADDR 0x2FFC0078
|
|
||||||
#define BOOTROM_MODE_MASK GENMASK(15, 0)
|
|
||||||
#define BOOTROM_MODE_SHIFT 0
|
|
||||||
#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
|
|
||||||
#define BOOTROM_INSTANCE_SHIFT 16
|
|
||||||
|
|
||||||
/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
|
|
||||||
#define RPN_SHIFT 0
|
|
||||||
#define RPN_MASK GENMASK(7, 0)
|
|
||||||
|
|
||||||
/* Package = bit 27:29 of OTP16
|
|
||||||
* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
|
|
||||||
* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
|
|
||||||
* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
|
|
||||||
* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
|
|
||||||
* - others: Reserved
|
|
||||||
*/
|
|
||||||
#define PKG_SHIFT 27
|
|
||||||
#define PKG_MASK GENMASK(2, 0)
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* early TLB into the .data section so that it not get cleared
|
* early TLB into the .data section so that it not get cleared
|
||||||
* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
|
* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
|
||||||
@ -93,121 +31,6 @@ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
|
|||||||
|
|
||||||
struct lmb lmb;
|
struct lmb lmb;
|
||||||
|
|
||||||
static void security_init(void)
|
|
||||||
{
|
|
||||||
/* Disable the backup domain write protection */
|
|
||||||
/* the protection is enable at each reset by hardware */
|
|
||||||
/* And must be disable by software */
|
|
||||||
setbits_le32(PWR_CR1, PWR_CR1_DBP);
|
|
||||||
|
|
||||||
while (!(readl(PWR_CR1) & PWR_CR1_DBP))
|
|
||||||
;
|
|
||||||
|
|
||||||
/* If RTC clock isn't enable so this is a cold boot then we need
|
|
||||||
* to reset the backup domain
|
|
||||||
*/
|
|
||||||
if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
|
|
||||||
setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
|
||||||
while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
|
|
||||||
;
|
|
||||||
clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* allow non secure access in Write/Read for all peripheral */
|
|
||||||
writel(GENMASK(25, 0), ETZPC_DECPROT0);
|
|
||||||
|
|
||||||
/* Open SYSRAM for no secure access */
|
|
||||||
writel(0x0, ETZPC_TZMA1_SIZE);
|
|
||||||
|
|
||||||
/* enable TZC1 TZC2 clock */
|
|
||||||
writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
|
|
||||||
|
|
||||||
/* Region 0 set to no access by default */
|
|
||||||
/* bit 0 / 16 => nsaid0 read/write Enable
|
|
||||||
* bit 1 / 17 => nsaid1 read/write Enable
|
|
||||||
* ...
|
|
||||||
* bit 15 / 31 => nsaid15 read/write Enable
|
|
||||||
*/
|
|
||||||
writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
|
|
||||||
/* bit 30 / 31 => Secure Global Enable : write/read */
|
|
||||||
/* bit 0 / 1 => Region Enable for filter 0/1 */
|
|
||||||
writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
|
|
||||||
|
|
||||||
/* Enable Filter 0 and 1 */
|
|
||||||
setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
|
|
||||||
|
|
||||||
/* RCC trust zone deactivated */
|
|
||||||
writel(0x0, RCC_TZCR);
|
|
||||||
|
|
||||||
/* TAMP: deactivate the internal tamper
|
|
||||||
* Bit 23 ITAMP8E: monotonic counter overflow
|
|
||||||
* Bit 20 ITAMP5E: RTC calendar overflow
|
|
||||||
* Bit 19 ITAMP4E: HSE monitoring
|
|
||||||
* Bit 18 ITAMP3E: LSE monitoring
|
|
||||||
* Bit 16 ITAMP1E: RTC power domain supply monitoring
|
|
||||||
*/
|
|
||||||
writel(0x0, TAMP_CR1);
|
|
||||||
|
|
||||||
/* GPIOZ: deactivate the security */
|
|
||||||
writel(BIT(0), RCC_MP_AHB5ENSETR);
|
|
||||||
writel(0x0, GPIOZ_SECCFGR);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Debug init
|
|
||||||
*/
|
|
||||||
static void dbgmcu_init(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Freeze IWDG2 if Cortex-A7 is in debug mode
|
|
||||||
* done in TF-A for TRUSTED boot and
|
|
||||||
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
|
|
||||||
*/
|
|
||||||
if (bsec_dbgswenable()) {
|
|
||||||
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
|
||||||
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void spl_board_init(void)
|
|
||||||
{
|
|
||||||
struct udevice *dev;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
dbgmcu_init();
|
|
||||||
|
|
||||||
/* force probe of BSEC driver to shadow the upper OTP */
|
|
||||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
|
|
||||||
if (ret)
|
|
||||||
log_warning("BSEC probe failed: %d\n", ret);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* get bootmode from ROM code boot context: saved in TAMP register */
|
|
||||||
static void update_bootmode(void)
|
|
||||||
{
|
|
||||||
u32 boot_mode;
|
|
||||||
u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
|
|
||||||
u32 bootrom_device, bootrom_instance;
|
|
||||||
|
|
||||||
/* enable TAMP clock = RTCAPBEN */
|
|
||||||
writel(BIT(8), RCC_MP_APB5ENSETR);
|
|
||||||
|
|
||||||
/* read bootrom context */
|
|
||||||
bootrom_device =
|
|
||||||
(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
|
|
||||||
bootrom_instance =
|
|
||||||
(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
|
|
||||||
boot_mode =
|
|
||||||
((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
|
|
||||||
((bootrom_instance << BOOT_INSTANCE_SHIFT) &
|
|
||||||
BOOT_INSTANCE_MASK);
|
|
||||||
|
|
||||||
/* save the boot mode in TAMP backup register */
|
|
||||||
clrsetbits_le32(TAMP_BOOT_CONTEXT,
|
|
||||||
TAMP_BOOT_MODE_MASK,
|
|
||||||
boot_mode << TAMP_BOOT_MODE_SHIFT);
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 get_bootmode(void)
|
u32 get_bootmode(void)
|
||||||
{
|
{
|
||||||
/* read bootmode from TAMP backup register */
|
/* read bootmode from TAMP backup register */
|
||||||
@ -229,8 +52,11 @@ void dram_bank_mmu_setup(int bank)
|
|||||||
enum dcache_option option;
|
enum dcache_option option;
|
||||||
|
|
||||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||||
|
/* STM32_SYSRAM_BASE exist only when SPL is supported */
|
||||||
|
#ifdef CONFIG_SPL
|
||||||
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
|
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
|
||||||
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
|
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
|
||||||
|
#endif
|
||||||
} else if (gd->flags & GD_FLG_RELOC) {
|
} else if (gd->flags & GD_FLG_RELOC) {
|
||||||
/* bd->bi_dram is available only after relocation */
|
/* bd->bi_dram is available only after relocation */
|
||||||
start = bd->bi_dram[bank].start;
|
start = bd->bi_dram[bank].start;
|
||||||
@ -277,26 +103,25 @@ static void early_enable_caches(void)
|
|||||||
*/
|
*/
|
||||||
int arch_cpu_init(void)
|
int arch_cpu_init(void)
|
||||||
{
|
{
|
||||||
u32 boot_mode;
|
|
||||||
|
|
||||||
early_enable_caches();
|
early_enable_caches();
|
||||||
|
|
||||||
/* early armv7 timer init: needed for polling */
|
/* early armv7 timer init: needed for polling */
|
||||||
timer_init();
|
timer_init();
|
||||||
|
|
||||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
return 0;
|
||||||
security_init();
|
|
||||||
update_bootmode();
|
|
||||||
}
|
|
||||||
/* reset copro state in SPL, when used, or in U-Boot */
|
|
||||||
if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
|
|
||||||
/* Reset Coprocessor state unless it wakes up from Standby power mode */
|
|
||||||
if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
|
|
||||||
writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
|
|
||||||
writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* weak function for SOC specific initialization */
|
||||||
|
__weak void stm32mp_cpu_init(void)
|
||||||
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int mach_cpu_init(void)
|
||||||
|
{
|
||||||
|
u32 boot_mode;
|
||||||
|
|
||||||
|
stm32mp_cpu_init();
|
||||||
|
|
||||||
boot_mode = get_bootmode();
|
boot_mode = get_bootmode();
|
||||||
|
|
||||||
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
|
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
|
||||||
@ -324,139 +149,6 @@ void enable_caches(void)
|
|||||||
dcache_enable();
|
dcache_enable();
|
||||||
}
|
}
|
||||||
|
|
||||||
static u32 read_idc(void)
|
|
||||||
{
|
|
||||||
/* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
|
|
||||||
if (bsec_dbgswenable()) {
|
|
||||||
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
|
||||||
|
|
||||||
return readl(DBGMCU_IDC);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (CONFIG_IS_ENABLED(STM32MP15x))
|
|
||||||
return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
|
|
||||||
else
|
|
||||||
return 0x0;
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 get_cpu_dev(void)
|
|
||||||
{
|
|
||||||
return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 get_cpu_rev(void)
|
|
||||||
{
|
|
||||||
return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
|
|
||||||
}
|
|
||||||
|
|
||||||
static u32 get_otp(int index, int shift, int mask)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
struct udevice *dev;
|
|
||||||
u32 otp = 0;
|
|
||||||
|
|
||||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
|
||||||
DM_DRIVER_GET(stm32mp_bsec),
|
|
||||||
&dev);
|
|
||||||
|
|
||||||
if (!ret)
|
|
||||||
ret = misc_read(dev, STM32_BSEC_SHADOW(index),
|
|
||||||
&otp, sizeof(otp));
|
|
||||||
|
|
||||||
return (otp >> shift) & mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get Device Part Number (RPN) from OTP */
|
|
||||||
static u32 get_cpu_rpn(void)
|
|
||||||
{
|
|
||||||
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 get_cpu_type(void)
|
|
||||||
{
|
|
||||||
return (get_cpu_dev() << 16) | get_cpu_rpn();
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get Package options from OTP */
|
|
||||||
u32 get_cpu_package(void)
|
|
||||||
{
|
|
||||||
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const char * const soc_type[] = {
|
|
||||||
"????",
|
|
||||||
"151C", "151A", "151F", "151D",
|
|
||||||
"153C", "153A", "153F", "153D",
|
|
||||||
"157C", "157A", "157F", "157D"
|
|
||||||
};
|
|
||||||
|
|
||||||
static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
|
|
||||||
static const char * const soc_rev[] = { "?", "A", "B", "Z" };
|
|
||||||
|
|
||||||
static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
|
|
||||||
unsigned int *rev)
|
|
||||||
{
|
|
||||||
u32 cpu_type = get_cpu_type();
|
|
||||||
u32 ct = cpu_type & ~(BIT(7) | BIT(0));
|
|
||||||
u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
|
|
||||||
u32 cp = get_cpu_package();
|
|
||||||
|
|
||||||
/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
|
|
||||||
switch (ct) {
|
|
||||||
case CPU_STM32MP151Cxx:
|
|
||||||
*type = cm + 1;
|
|
||||||
break;
|
|
||||||
case CPU_STM32MP153Cxx:
|
|
||||||
*type = cm + 5;
|
|
||||||
break;
|
|
||||||
case CPU_STM32MP157Cxx:
|
|
||||||
*type = cm + 9;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
*type = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Package */
|
|
||||||
switch (cp) {
|
|
||||||
case PKG_AA_LBGA448:
|
|
||||||
case PKG_AB_LBGA354:
|
|
||||||
case PKG_AC_TFBGA361:
|
|
||||||
case PKG_AD_TFBGA257:
|
|
||||||
*pkg = cp;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
*pkg = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Revision */
|
|
||||||
switch (get_cpu_rev()) {
|
|
||||||
case CPU_REV1:
|
|
||||||
*rev = 1;
|
|
||||||
break;
|
|
||||||
case CPU_REV2:
|
|
||||||
*rev = 2;
|
|
||||||
break;
|
|
||||||
case CPU_REV2_1:
|
|
||||||
*rev = 3;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
*rev = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void get_soc_name(char name[SOC_NAME_SIZE])
|
|
||||||
{
|
|
||||||
unsigned int type, pkg, rev;
|
|
||||||
|
|
||||||
get_cpu_string_offsets(&type, &pkg, &rev);
|
|
||||||
|
|
||||||
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
|
|
||||||
soc_type[type], soc_pkg[pkg], soc_rev[rev]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* used when CONFIG_DISPLAY_CPUINFO is activated */
|
/* used when CONFIG_DISPLAY_CPUINFO is activated */
|
||||||
int print_cpuinfo(void)
|
int print_cpuinfo(void)
|
||||||
{
|
{
|
||||||
@ -598,16 +290,18 @@ __weak int setup_mac_address(void)
|
|||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
int i;
|
int i;
|
||||||
u32 otp[2];
|
u32 otp[3];
|
||||||
uchar enetaddr[6];
|
uchar enetaddr[6];
|
||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
|
int nb_eth, nb_otp, index;
|
||||||
|
|
||||||
if (!IS_ENABLED(CONFIG_NET))
|
if (!IS_ENABLED(CONFIG_NET))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
/* MAC already in environment */
|
nb_eth = get_eth_nb();
|
||||||
if (eth_env_get_enetaddr("ethaddr", enetaddr))
|
|
||||||
return 0;
|
/* 6 bytes for each MAC addr and 4 bytes for each OTP */
|
||||||
|
nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);
|
||||||
|
|
||||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||||
DM_DRIVER_GET(stm32mp_bsec),
|
DM_DRIVER_GET(stm32mp_bsec),
|
||||||
@ -615,22 +309,31 @@ __weak int setup_mac_address(void)
|
|||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
|
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
|
||||||
otp, sizeof(otp));
|
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
|
for (index = 0; index < nb_eth; index++) {
|
||||||
|
/* MAC already in environment */
|
||||||
|
if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
|
||||||
|
continue;
|
||||||
|
|
||||||
for (i = 0; i < 6; i++)
|
for (i = 0; i < 6; i++)
|
||||||
enetaddr[i] = ((uint8_t *)&otp)[i];
|
enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index];
|
||||||
|
|
||||||
if (!is_valid_ethaddr(enetaddr)) {
|
if (!is_valid_ethaddr(enetaddr)) {
|
||||||
log_err("invalid MAC address in OTP %pM\n", enetaddr);
|
log_err("invalid MAC address %d in OTP %pM\n",
|
||||||
|
index, enetaddr);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
log_debug("OTP MAC address = %pM\n", enetaddr);
|
log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
|
||||||
ret = eth_env_set_enetaddr("ethaddr", enetaddr);
|
ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
|
||||||
if (ret)
|
if (ret) {
|
||||||
log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
|
log_err("Failed to set mac address %pM from OTP: %d\n",
|
||||||
|
enetaddr, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -662,15 +365,8 @@ static int setup_serial_number(void)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void setup_soc_type_pkg_rev(void)
|
__weak void stm32mp_misc_init(void)
|
||||||
{
|
{
|
||||||
unsigned int type, pkg, rev;
|
|
||||||
|
|
||||||
get_cpu_string_offsets(&type, &pkg, &rev);
|
|
||||||
|
|
||||||
env_set("soc_type", soc_type[type]);
|
|
||||||
env_set("soc_pkg", soc_pkg[pkg]);
|
|
||||||
env_set("soc_rev", soc_rev[rev]);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int arch_misc_init(void)
|
int arch_misc_init(void)
|
||||||
@ -678,7 +374,7 @@ int arch_misc_init(void)
|
|||||||
setup_boot_mode();
|
setup_boot_mode();
|
||||||
setup_mac_address();
|
setup_mac_address();
|
||||||
setup_serial_number();
|
setup_serial_number();
|
||||||
setup_soc_type_pkg_rev();
|
stm32mp_misc_init();
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|||||||
@ -28,13 +28,120 @@
|
|||||||
|
|
||||||
#define ETZPC_RESERVED 0xffffffff
|
#define ETZPC_RESERVED 0xffffffff
|
||||||
|
|
||||||
#define STM32_FDCAN_BASE 0x4400e000
|
#define STM32MP13_FDCAN_BASE 0x4400F000
|
||||||
#define STM32_CRYP2_BASE 0x4c005000
|
#define STM32MP13_ADC1_BASE 0x48003000
|
||||||
#define STM32_CRYP1_BASE 0x54001000
|
#define STM32MP13_TSC_BASE 0x5000B000
|
||||||
#define STM32_GPU_BASE 0x59000000
|
#define STM32MP13_CRYP_BASE 0x54002000
|
||||||
#define STM32_DSI_BASE 0x5a000000
|
#define STM32MP13_ETH2_BASE 0x5800E000
|
||||||
|
#define STM32MP13_DCMIPP_BASE 0x5A000000
|
||||||
|
#define STM32MP13_LTDC_BASE 0x5A010000
|
||||||
|
|
||||||
static const u32 stm32mp1_ip_addr[] = {
|
#define STM32MP15_FDCAN_BASE 0x4400e000
|
||||||
|
#define STM32MP15_CRYP2_BASE 0x4c005000
|
||||||
|
#define STM32MP15_CRYP1_BASE 0x54001000
|
||||||
|
#define STM32MP15_GPU_BASE 0x59000000
|
||||||
|
#define STM32MP15_DSI_BASE 0x5a000000
|
||||||
|
|
||||||
|
static const u32 stm32mp13_ip_addr[] = {
|
||||||
|
0x50025000, /* 0 VREFBUF APB3 */
|
||||||
|
0x50021000, /* 1 LPTIM2 APB3 */
|
||||||
|
0x50022000, /* 2 LPTIM3 APB3 */
|
||||||
|
STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
|
||||||
|
STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
|
||||||
|
0x5A006000, /* 5 USBPHYCTRL APB4 */
|
||||||
|
0x5A003000, /* 6 DDRCTRLPHY APB4 */
|
||||||
|
ETZPC_RESERVED, /* 7 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 8 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 9 Reserved*/
|
||||||
|
0x5C006000, /* 10 TZC APB5 */
|
||||||
|
0x58001000, /* 11 MCE APB5 */
|
||||||
|
0x5C000000, /* 12 IWDG1 APB5 */
|
||||||
|
0x5C008000, /* 13 STGENC APB5 */
|
||||||
|
ETZPC_RESERVED, /* 14 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 15 Reserved*/
|
||||||
|
0x4C000000, /* 16 USART1 APB6 */
|
||||||
|
0x4C001000, /* 17 USART2 APB6 */
|
||||||
|
0x4C002000, /* 18 SPI4 APB6 */
|
||||||
|
0x4C003000, /* 19 SPI5 APB6 */
|
||||||
|
0x4C004000, /* 20 I2C3 APB6 */
|
||||||
|
0x4C005000, /* 21 I2C4 APB6 */
|
||||||
|
0x4C006000, /* 22 I2C5 APB6 */
|
||||||
|
0x4C007000, /* 23 TIM12 APB6 */
|
||||||
|
0x4C008000, /* 24 TIM13 APB6 */
|
||||||
|
0x4C009000, /* 25 TIM14 APB6 */
|
||||||
|
0x4C00A000, /* 26 TIM15 APB6 */
|
||||||
|
0x4C00B000, /* 27 TIM16 APB6 */
|
||||||
|
0x4C00C000, /* 28 TIM17 APB6 */
|
||||||
|
ETZPC_RESERVED, /* 29 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 30 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 31 Reserved*/
|
||||||
|
STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
|
||||||
|
0x48004000, /* 33 ADC2 AHB2 */
|
||||||
|
0x49000000, /* 34 OTG AHB2 */
|
||||||
|
ETZPC_RESERVED, /* 35 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 36 Reserved*/
|
||||||
|
STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
|
||||||
|
ETZPC_RESERVED, /* 38 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 39 Reserved*/
|
||||||
|
0x54004000, /* 40 RNG AHB5 */
|
||||||
|
0x54003000, /* 41 HASH AHB5 */
|
||||||
|
STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
|
||||||
|
0x54005000, /* 43 SAES AHB5 */
|
||||||
|
0x54006000, /* 44 PKA AHB5 */
|
||||||
|
0x54000000, /* 45 BKPSRAM AHB5 */
|
||||||
|
ETZPC_RESERVED, /* 46 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 47 Reserved*/
|
||||||
|
0x5800A000, /* 48 ETH1 AHB6 */
|
||||||
|
STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
|
||||||
|
0x58005000, /* 50 SDMMC1 AHB6 */
|
||||||
|
0x58007000, /* 51 SDMMC2 AHB6 */
|
||||||
|
ETZPC_RESERVED, /* 52 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 53 Reserved*/
|
||||||
|
0x58002000, /* 54 FMC AHB6 */
|
||||||
|
0x58003000, /* 55 QSPI AHB6 */
|
||||||
|
ETZPC_RESERVED, /* 56 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 57 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 58 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 59 Reserved*/
|
||||||
|
0x30000000, /* 60 SRAM1 MLAHB */
|
||||||
|
0x30004000, /* 61 SRAM2 MLAHB */
|
||||||
|
0x30006000, /* 62 SRAM3 MLAHB */
|
||||||
|
ETZPC_RESERVED, /* 63 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 64 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 65 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 66 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 67 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 68 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 69 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 70 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 71 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 72 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 73 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 74 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 75 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 76 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 77 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 78 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 79 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 80 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 81 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 82 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 83 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 84 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 85 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 86 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 87 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 88 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 89 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 90 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 91 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 92 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 93 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 94 Reserved*/
|
||||||
|
ETZPC_RESERVED, /* 95 Reserved*/
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u32 stm32mp15_ip_addr[] = {
|
||||||
0x5c008000, /* 00 stgenc */
|
0x5c008000, /* 00 stgenc */
|
||||||
0x54000000, /* 01 bkpsram */
|
0x54000000, /* 01 bkpsram */
|
||||||
0x5c003000, /* 02 iwdg1 */
|
0x5c003000, /* 02 iwdg1 */
|
||||||
@ -44,7 +151,7 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||||||
ETZPC_RESERVED, /* 06 reserved */
|
ETZPC_RESERVED, /* 06 reserved */
|
||||||
0x54003000, /* 07 rng1 */
|
0x54003000, /* 07 rng1 */
|
||||||
0x54002000, /* 08 hash1 */
|
0x54002000, /* 08 hash1 */
|
||||||
STM32_CRYP1_BASE, /* 09 cryp1 */
|
STM32MP15_CRYP1_BASE, /* 09 cryp1 */
|
||||||
0x5a003000, /* 0A ddrctrl */
|
0x5a003000, /* 0A ddrctrl */
|
||||||
0x5a004000, /* 0B ddrphyc */
|
0x5a004000, /* 0B ddrphyc */
|
||||||
0x5c009000, /* 0C i2c6 */
|
0x5c009000, /* 0C i2c6 */
|
||||||
@ -97,7 +204,7 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||||||
0x4400b000, /* 3B sai2 */
|
0x4400b000, /* 3B sai2 */
|
||||||
0x4400c000, /* 3C sai3 */
|
0x4400c000, /* 3C sai3 */
|
||||||
0x4400d000, /* 3D dfsdm */
|
0x4400d000, /* 3D dfsdm */
|
||||||
STM32_FDCAN_BASE, /* 3E tt_fdcan */
|
STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
|
||||||
ETZPC_RESERVED, /* 3F reserved */
|
ETZPC_RESERVED, /* 3F reserved */
|
||||||
0x50021000, /* 40 lptim2 */
|
0x50021000, /* 40 lptim2 */
|
||||||
0x50022000, /* 41 lptim3 */
|
0x50022000, /* 41 lptim3 */
|
||||||
@ -110,7 +217,7 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||||||
0x48003000, /* 48 adc */
|
0x48003000, /* 48 adc */
|
||||||
0x4c002000, /* 49 hash2 */
|
0x4c002000, /* 49 hash2 */
|
||||||
0x4c003000, /* 4A rng2 */
|
0x4c003000, /* 4A rng2 */
|
||||||
STM32_CRYP2_BASE, /* 4B cryp2 */
|
STM32MP15_CRYP2_BASE, /* 4B cryp2 */
|
||||||
ETZPC_RESERVED, /* 4C reserved */
|
ETZPC_RESERVED, /* 4C reserved */
|
||||||
ETZPC_RESERVED, /* 4D reserved */
|
ETZPC_RESERVED, /* 4D reserved */
|
||||||
ETZPC_RESERVED, /* 4E reserved */
|
ETZPC_RESERVED, /* 4E reserved */
|
||||||
@ -163,8 +270,15 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
|
|||||||
int offset, shift;
|
int offset, shift;
|
||||||
u32 addr, status, decprot[ETZPC_DECPROT_NB];
|
u32 addr, status, decprot[ETZPC_DECPROT_NB];
|
||||||
|
|
||||||
array = stm32mp1_ip_addr;
|
if (IS_ENABLED(CONFIG_STM32MP13x)) {
|
||||||
array_size = ARRAY_SIZE(stm32mp1_ip_addr);
|
array = stm32mp13_ip_addr;
|
||||||
|
array_size = ARRAY_SIZE(stm32mp13_ip_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_STM32MP15x)) {
|
||||||
|
array = stm32mp15_ip_addr;
|
||||||
|
array_size = ARRAY_SIZE(stm32mp15_ip_addr);
|
||||||
|
}
|
||||||
|
|
||||||
for (i = 0; i < ETZPC_DECPROT_NB; i++)
|
for (i = 0; i < ETZPC_DECPROT_NB; i++)
|
||||||
decprot[i] = readl(ETZPC_DECPROT(i));
|
decprot[i] = readl(ETZPC_DECPROT(i));
|
||||||
@ -248,6 +362,107 @@ static void stm32_fdt_disable_optee(void *blob)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
|
||||||
|
{
|
||||||
|
switch (cpu) {
|
||||||
|
case CPU_STM32MP131Fxx:
|
||||||
|
case CPU_STM32MP131Dxx:
|
||||||
|
case CPU_STM32MP131Cxx:
|
||||||
|
case CPU_STM32MP131Axx:
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
|
||||||
|
fallthrough;
|
||||||
|
case CPU_STM32MP133Fxx:
|
||||||
|
case CPU_STM32MP133Dxx:
|
||||||
|
case CPU_STM32MP133Cxx:
|
||||||
|
case CPU_STM32MP133Axx:
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
|
||||||
|
name);
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (cpu) {
|
||||||
|
case CPU_STM32MP135Dxx:
|
||||||
|
case CPU_STM32MP135Axx:
|
||||||
|
case CPU_STM32MP133Dxx:
|
||||||
|
case CPU_STM32MP133Axx:
|
||||||
|
case CPU_STM32MP131Dxx:
|
||||||
|
case CPU_STM32MP131Axx:
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
|
||||||
|
{
|
||||||
|
u32 pkg;
|
||||||
|
|
||||||
|
switch (cpu) {
|
||||||
|
case CPU_STM32MP151Fxx:
|
||||||
|
case CPU_STM32MP151Dxx:
|
||||||
|
case CPU_STM32MP151Cxx:
|
||||||
|
case CPU_STM32MP151Axx:
|
||||||
|
stm32_fdt_fixup_cpu(blob, name);
|
||||||
|
/* after cpu delete we can't trust the soc offsets anymore */
|
||||||
|
soc = fdt_path_offset(blob, "/soc");
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
|
||||||
|
fallthrough;
|
||||||
|
case CPU_STM32MP153Fxx:
|
||||||
|
case CPU_STM32MP153Dxx:
|
||||||
|
case CPU_STM32MP153Cxx:
|
||||||
|
case CPU_STM32MP153Axx:
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
switch (cpu) {
|
||||||
|
case CPU_STM32MP157Dxx:
|
||||||
|
case CPU_STM32MP157Axx:
|
||||||
|
case CPU_STM32MP153Dxx:
|
||||||
|
case CPU_STM32MP153Axx:
|
||||||
|
case CPU_STM32MP151Dxx:
|
||||||
|
case CPU_STM32MP151Axx:
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
|
||||||
|
name);
|
||||||
|
stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
|
||||||
|
name);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
switch (get_cpu_package()) {
|
||||||
|
case STM32MP15_PKG_AA_LBGA448:
|
||||||
|
pkg = STM32MP_PKG_AA;
|
||||||
|
break;
|
||||||
|
case STM32MP15_PKG_AB_LBGA354:
|
||||||
|
pkg = STM32MP_PKG_AB;
|
||||||
|
break;
|
||||||
|
case STM32MP15_PKG_AC_TFBGA361:
|
||||||
|
pkg = STM32MP_PKG_AC;
|
||||||
|
break;
|
||||||
|
case STM32MP15_PKG_AD_TFBGA257:
|
||||||
|
pkg = STM32MP_PKG_AD;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
pkg = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (pkg) {
|
||||||
|
do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
|
||||||
|
"st,package", pkg, false);
|
||||||
|
do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
|
||||||
|
"st,package", pkg, false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This function is called right before the kernel is booted. "blob" is the
|
* This function is called right before the kernel is booted. "blob" is the
|
||||||
* device tree that will be passed to the kernel.
|
* device tree that will be passed to the kernel.
|
||||||
@ -256,7 +471,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
|||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
int soc;
|
int soc;
|
||||||
u32 pkg, cpu;
|
u32 cpu;
|
||||||
char name[SOC_NAME_SIZE];
|
char name[SOC_NAME_SIZE];
|
||||||
|
|
||||||
soc = fdt_path_offset(blob, "/soc");
|
soc = fdt_path_offset(blob, "/soc");
|
||||||
@ -276,64 +491,11 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
|||||||
cpu = get_cpu_type();
|
cpu = get_cpu_type();
|
||||||
get_soc_name(name);
|
get_soc_name(name);
|
||||||
|
|
||||||
switch (cpu) {
|
if (IS_ENABLED(CONFIG_STM32MP13x))
|
||||||
case CPU_STM32MP151Fxx:
|
stm32mp13_fdt_fixup(blob, soc, cpu, name);
|
||||||
case CPU_STM32MP151Dxx:
|
|
||||||
case CPU_STM32MP151Cxx:
|
|
||||||
case CPU_STM32MP151Axx:
|
|
||||||
stm32_fdt_fixup_cpu(blob, name);
|
|
||||||
/* after cpu delete we can't trust the soc offsets anymore */
|
|
||||||
soc = fdt_path_offset(blob, "/soc");
|
|
||||||
stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
|
|
||||||
/* fall through */
|
|
||||||
case CPU_STM32MP153Fxx:
|
|
||||||
case CPU_STM32MP153Dxx:
|
|
||||||
case CPU_STM32MP153Cxx:
|
|
||||||
case CPU_STM32MP153Axx:
|
|
||||||
stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
|
|
||||||
stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (cpu) {
|
if (IS_ENABLED(CONFIG_STM32MP15x)) {
|
||||||
case CPU_STM32MP157Dxx:
|
stm32mp15_fdt_fixup(blob, soc, cpu, name);
|
||||||
case CPU_STM32MP157Axx:
|
|
||||||
case CPU_STM32MP153Dxx:
|
|
||||||
case CPU_STM32MP153Axx:
|
|
||||||
case CPU_STM32MP151Dxx:
|
|
||||||
case CPU_STM32MP151Axx:
|
|
||||||
stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
|
|
||||||
stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (get_cpu_package()) {
|
|
||||||
case PKG_AA_LBGA448:
|
|
||||||
pkg = STM32MP_PKG_AA;
|
|
||||||
break;
|
|
||||||
case PKG_AB_LBGA354:
|
|
||||||
pkg = STM32MP_PKG_AB;
|
|
||||||
break;
|
|
||||||
case PKG_AC_TFBGA361:
|
|
||||||
pkg = STM32MP_PKG_AC;
|
|
||||||
break;
|
|
||||||
case PKG_AD_TFBGA257:
|
|
||||||
pkg = STM32MP_PKG_AD;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
pkg = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (pkg) {
|
|
||||||
do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
|
|
||||||
"st,package", pkg, false);
|
|
||||||
do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
|
|
||||||
"st,package", pkg, false);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TEMP: remove OP-TEE nodes in kernel device tree
|
* TEMP: remove OP-TEE nodes in kernel device tree
|
||||||
@ -346,6 +508,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
|||||||
if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
|
if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
|
||||||
!tee_find_device(NULL, NULL, NULL, NULL))
|
!tee_find_device(NULL, NULL, NULL, NULL))
|
||||||
stm32_fdt_disable_optee(blob);
|
stm32_fdt_disable_optee(blob);
|
||||||
|
}
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|||||||
@ -17,7 +17,9 @@
|
|||||||
#define STM32_RCC_BASE 0x50000000
|
#define STM32_RCC_BASE 0x50000000
|
||||||
#define STM32_PWR_BASE 0x50001000
|
#define STM32_PWR_BASE 0x50001000
|
||||||
#define STM32_SYSCFG_BASE 0x50020000
|
#define STM32_SYSCFG_BASE 0x50020000
|
||||||
|
#ifdef CONFIG_STM32MP15x
|
||||||
#define STM32_DBGMCU_BASE 0x50081000
|
#define STM32_DBGMCU_BASE 0x50081000
|
||||||
|
#endif
|
||||||
#define STM32_FMC2_BASE 0x58002000
|
#define STM32_FMC2_BASE 0x58002000
|
||||||
#define STM32_DDRCTRL_BASE 0x5A003000
|
#define STM32_DDRCTRL_BASE 0x5A003000
|
||||||
#define STM32_DDRPHYC_BASE 0x5A004000
|
#define STM32_DDRPHYC_BASE 0x5A004000
|
||||||
@ -26,8 +28,14 @@
|
|||||||
#define STM32_STGEN_BASE 0x5C008000
|
#define STM32_STGEN_BASE 0x5C008000
|
||||||
#define STM32_TAMP_BASE 0x5C00A000
|
#define STM32_TAMP_BASE 0x5C00A000
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32MP15x
|
||||||
#define STM32_USART1_BASE 0x5C000000
|
#define STM32_USART1_BASE 0x5C000000
|
||||||
#define STM32_USART2_BASE 0x4000E000
|
#define STM32_USART2_BASE 0x4000E000
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_STM32MP13x
|
||||||
|
#define STM32_USART1_BASE 0x4c000000
|
||||||
|
#define STM32_USART2_BASE 0x4c001000
|
||||||
|
#endif
|
||||||
#define STM32_USART3_BASE 0x4000F000
|
#define STM32_USART3_BASE 0x4000F000
|
||||||
#define STM32_UART4_BASE 0x40010000
|
#define STM32_UART4_BASE 0x40010000
|
||||||
#define STM32_UART5_BASE 0x40011000
|
#define STM32_UART5_BASE 0x40011000
|
||||||
@ -39,8 +47,10 @@
|
|||||||
#define STM32_SDMMC2_BASE 0x58007000
|
#define STM32_SDMMC2_BASE 0x58007000
|
||||||
#define STM32_SDMMC3_BASE 0x48004000
|
#define STM32_SDMMC3_BASE 0x48004000
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32MP15x
|
||||||
#define STM32_SYSRAM_BASE 0x2FFC0000
|
#define STM32_SYSRAM_BASE 0x2FFC0000
|
||||||
#define STM32_SYSRAM_SIZE SZ_256K
|
#define STM32_SYSRAM_SIZE SZ_256K
|
||||||
|
#endif
|
||||||
|
|
||||||
#define STM32_DDR_BASE 0xC0000000
|
#define STM32_DDR_BASE 0xC0000000
|
||||||
#define STM32_DDR_SIZE SZ_1G
|
#define STM32_DDR_SIZE SZ_1G
|
||||||
@ -98,6 +108,8 @@ enum boot_device {
|
|||||||
|
|
||||||
/* TAMP registers */
|
/* TAMP registers */
|
||||||
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
|
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32MP15x
|
||||||
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
|
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
|
||||||
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
|
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
|
||||||
#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
|
#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
|
||||||
@ -111,13 +123,18 @@ enum boot_device {
|
|||||||
#define TAMP_COPRO_STATE_CSTOP 3
|
#define TAMP_COPRO_STATE_CSTOP 3
|
||||||
#define TAMP_COPRO_STATE_STANDBY 4
|
#define TAMP_COPRO_STATE_STANDBY 4
|
||||||
#define TAMP_COPRO_STATE_CRASH 5
|
#define TAMP_COPRO_STATE_CRASH 5
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32MP13x
|
||||||
|
#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31)
|
||||||
|
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
|
||||||
|
#endif
|
||||||
|
|
||||||
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
|
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
|
||||||
#define TAMP_BOOT_MODE_SHIFT 8
|
#define TAMP_BOOT_MODE_SHIFT 8
|
||||||
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
|
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
|
||||||
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
|
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
|
||||||
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
|
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
|
||||||
#define TAMP_BOOT_DEBUG_ON BIT(16)
|
|
||||||
|
|
||||||
enum forced_boot_mode {
|
enum forced_boot_mode {
|
||||||
BOOT_NORMAL = 0x00,
|
BOOT_NORMAL = 0x00,
|
||||||
@ -138,11 +155,19 @@ enum forced_boot_mode {
|
|||||||
#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
|
#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
|
||||||
|
|
||||||
/* BSEC OTP index */
|
/* BSEC OTP index */
|
||||||
|
#ifdef CONFIG_STM32MP15x
|
||||||
#define BSEC_OTP_RPN 1
|
#define BSEC_OTP_RPN 1
|
||||||
#define BSEC_OTP_SERIAL 13
|
#define BSEC_OTP_SERIAL 13
|
||||||
#define BSEC_OTP_PKG 16
|
#define BSEC_OTP_PKG 16
|
||||||
#define BSEC_OTP_MAC 57
|
#define BSEC_OTP_MAC 57
|
||||||
#define BSEC_OTP_BOARD 59
|
#define BSEC_OTP_BOARD 59
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_STM32MP13x
|
||||||
|
#define BSEC_OTP_RPN 1
|
||||||
|
#define BSEC_OTP_SERIAL 13
|
||||||
|
#define BSEC_OTP_MAC 57
|
||||||
|
#define BSEC_OTP_BOARD 60
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* __ASSEMBLY__ */
|
#endif /* __ASSEMBLY__ */
|
||||||
#endif /* _MACH_STM32_H_ */
|
#endif /* _MACH_STM32_H_ */
|
||||||
|
|||||||
@ -3,7 +3,7 @@
|
|||||||
* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
|
* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */
|
/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
|
||||||
#define CPU_STM32MP157Cxx 0x05000000
|
#define CPU_STM32MP157Cxx 0x05000000
|
||||||
#define CPU_STM32MP157Axx 0x05000001
|
#define CPU_STM32MP157Axx 0x05000001
|
||||||
#define CPU_STM32MP153Cxx 0x05000024
|
#define CPU_STM32MP153Cxx 0x05000024
|
||||||
@ -17,10 +17,24 @@
|
|||||||
#define CPU_STM32MP151Fxx 0x050000AE
|
#define CPU_STM32MP151Fxx 0x050000AE
|
||||||
#define CPU_STM32MP151Dxx 0x050000AF
|
#define CPU_STM32MP151Dxx 0x050000AF
|
||||||
|
|
||||||
|
#define CPU_STM32MP135Cxx 0x05010000
|
||||||
|
#define CPU_STM32MP135Axx 0x05010001
|
||||||
|
#define CPU_STM32MP133Cxx 0x050100C0
|
||||||
|
#define CPU_STM32MP133Axx 0x050100C1
|
||||||
|
#define CPU_STM32MP131Cxx 0x050106C8
|
||||||
|
#define CPU_STM32MP131Axx 0x050106C9
|
||||||
|
#define CPU_STM32MP135Fxx 0x05010800
|
||||||
|
#define CPU_STM32MP135Dxx 0x05010801
|
||||||
|
#define CPU_STM32MP133Fxx 0x050108C0
|
||||||
|
#define CPU_STM32MP133Dxx 0x050108C1
|
||||||
|
#define CPU_STM32MP131Fxx 0x05010EC8
|
||||||
|
#define CPU_STM32MP131Dxx 0x05010EC9
|
||||||
|
|
||||||
/* return CPU_STMP32MP...Xxx constants */
|
/* return CPU_STMP32MP...Xxx constants */
|
||||||
u32 get_cpu_type(void);
|
u32 get_cpu_type(void);
|
||||||
|
|
||||||
#define CPU_DEV_STM32MP15 0x500
|
#define CPU_DEV_STM32MP15 0x500
|
||||||
|
#define CPU_DEV_STM32MP13 0x501
|
||||||
|
|
||||||
/* return CPU_DEV constants */
|
/* return CPU_DEV constants */
|
||||||
u32 get_cpu_dev(void);
|
u32 get_cpu_dev(void);
|
||||||
@ -36,10 +50,12 @@ u32 get_cpu_rev(void);
|
|||||||
/* Get Package options from OTP */
|
/* Get Package options from OTP */
|
||||||
u32 get_cpu_package(void);
|
u32 get_cpu_package(void);
|
||||||
|
|
||||||
#define PKG_AA_LBGA448 4
|
/* package used for STM32MP15x */
|
||||||
#define PKG_AB_LBGA354 3
|
#define STM32MP15_PKG_AA_LBGA448 4
|
||||||
#define PKG_AC_TFBGA361 2
|
#define STM32MP15_PKG_AB_LBGA354 3
|
||||||
#define PKG_AD_TFBGA257 1
|
#define STM32MP15_PKG_AC_TFBGA361 2
|
||||||
|
#define STM32MP15_PKG_AD_TFBGA257 1
|
||||||
|
#define STM32MP15_PKG_UNKNOWN 0
|
||||||
|
|
||||||
/* Get SOC name */
|
/* Get SOC name */
|
||||||
#define SOC_NAME_SIZE 20
|
#define SOC_NAME_SIZE 20
|
||||||
@ -48,7 +64,15 @@ void get_soc_name(char name[SOC_NAME_SIZE]);
|
|||||||
/* return boot mode */
|
/* return boot mode */
|
||||||
u32 get_bootmode(void);
|
u32 get_bootmode(void);
|
||||||
|
|
||||||
|
int get_eth_nb(void);
|
||||||
int setup_mac_address(void);
|
int setup_mac_address(void);
|
||||||
|
|
||||||
/* board power management : configure vddcore according OPP */
|
/* board power management : configure vddcore according OPP */
|
||||||
void board_vddcore_init(u32 voltage_mv);
|
void board_vddcore_init(u32 voltage_mv);
|
||||||
|
|
||||||
|
/* weak function */
|
||||||
|
void stm32mp_cpu_init(void);
|
||||||
|
void stm32mp_misc_init(void);
|
||||||
|
|
||||||
|
/* helper function: read data from OTP */
|
||||||
|
u32 get_otp(int index, int shift, int mask);
|
||||||
|
|||||||
@ -190,6 +190,7 @@ void board_init_f(ulong dummy)
|
|||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
arch_cpu_init();
|
arch_cpu_init();
|
||||||
|
mach_cpu_init();
|
||||||
|
|
||||||
ret = spl_early_init();
|
ret = spl_early_init();
|
||||||
if (ret) {
|
if (ret) {
|
||||||
|
|||||||
135
arch/arm/mach-stm32mp/stm32mp13x.c
Normal file
135
arch/arm/mach-stm32mp/stm32mp13x.c
Normal file
@ -0,0 +1,135 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define LOG_CATEGORY LOGC_ARCH
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <log.h>
|
||||||
|
#include <syscon.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/stm32.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
|
||||||
|
/* SYSCFG register */
|
||||||
|
#define SYSCFG_IDC_OFFSET 0x380
|
||||||
|
#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
|
||||||
|
#define SYSCFG_IDC_DEV_ID_SHIFT 0
|
||||||
|
#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
|
||||||
|
#define SYSCFG_IDC_REV_ID_SHIFT 16
|
||||||
|
|
||||||
|
/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */
|
||||||
|
#define RPN_SHIFT 0
|
||||||
|
#define RPN_MASK GENMASK(11, 0)
|
||||||
|
|
||||||
|
static u32 read_idc(void)
|
||||||
|
{
|
||||||
|
void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
|
||||||
|
|
||||||
|
return readl(syscfg + SYSCFG_IDC_OFFSET);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_cpu_dev(void)
|
||||||
|
{
|
||||||
|
return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_cpu_rev(void)
|
||||||
|
{
|
||||||
|
return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get Device Part Number (RPN) from OTP */
|
||||||
|
static u32 get_cpu_rpn(void)
|
||||||
|
{
|
||||||
|
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_cpu_type(void)
|
||||||
|
{
|
||||||
|
return (get_cpu_dev() << 16) | get_cpu_rpn();
|
||||||
|
}
|
||||||
|
|
||||||
|
int get_eth_nb(void)
|
||||||
|
{
|
||||||
|
int nb_eth = 2;
|
||||||
|
|
||||||
|
switch (get_cpu_type()) {
|
||||||
|
case CPU_STM32MP131Dxx:
|
||||||
|
fallthrough;
|
||||||
|
case CPU_STM32MP131Cxx:
|
||||||
|
fallthrough;
|
||||||
|
case CPU_STM32MP131Axx:
|
||||||
|
nb_eth = 1;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
nb_eth = 2;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return nb_eth;
|
||||||
|
}
|
||||||
|
|
||||||
|
void get_soc_name(char name[SOC_NAME_SIZE])
|
||||||
|
{
|
||||||
|
char *cpu_s, *cpu_r;
|
||||||
|
|
||||||
|
/* MPUs Part Numbers */
|
||||||
|
switch (get_cpu_type()) {
|
||||||
|
case CPU_STM32MP135Fxx:
|
||||||
|
cpu_s = "135F";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP135Dxx:
|
||||||
|
cpu_s = "135D";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP135Cxx:
|
||||||
|
cpu_s = "135C";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP135Axx:
|
||||||
|
cpu_s = "135A";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP133Fxx:
|
||||||
|
cpu_s = "133F";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP133Dxx:
|
||||||
|
cpu_s = "133D";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP133Cxx:
|
||||||
|
cpu_s = "133C";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP133Axx:
|
||||||
|
cpu_s = "133A";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP131Fxx:
|
||||||
|
cpu_s = "131F";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP131Dxx:
|
||||||
|
cpu_s = "131D";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP131Cxx:
|
||||||
|
cpu_s = "131C";
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP131Axx:
|
||||||
|
cpu_s = "131A";
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
cpu_s = "????";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* REVISION */
|
||||||
|
switch (get_cpu_rev()) {
|
||||||
|
case CPU_REV1:
|
||||||
|
cpu_r = "A";
|
||||||
|
break;
|
||||||
|
case CPU_REV1_1:
|
||||||
|
cpu_r = "Z";
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
cpu_r = "?";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r);
|
||||||
|
}
|
||||||
350
arch/arm/mach-stm32mp/stm32mp15x.c
Normal file
350
arch/arm/mach-stm32mp/stm32mp15x.c
Normal file
@ -0,0 +1,350 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define LOG_CATEGORY LOGC_ARCH
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <env.h>
|
||||||
|
#include <log.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/bsec.h>
|
||||||
|
#include <asm/arch/stm32.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <dm/device.h>
|
||||||
|
#include <dm/uclass.h>
|
||||||
|
|
||||||
|
/* RCC register */
|
||||||
|
#define RCC_TZCR (STM32_RCC_BASE + 0x00)
|
||||||
|
#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
|
||||||
|
#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
|
||||||
|
#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
|
||||||
|
#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
|
||||||
|
|
||||||
|
#define RCC_BDCR_VSWRST BIT(31)
|
||||||
|
#define RCC_BDCR_RTCSRC GENMASK(17, 16)
|
||||||
|
|
||||||
|
#define RCC_DBGCFGR_DBGCKEN BIT(8)
|
||||||
|
|
||||||
|
/* DBGMCU register */
|
||||||
|
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
|
||||||
|
#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
|
||||||
|
#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
|
||||||
|
|
||||||
|
/* Security register */
|
||||||
|
#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
|
||||||
|
#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
|
||||||
|
|
||||||
|
#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
|
||||||
|
#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
|
||||||
|
#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
|
||||||
|
|
||||||
|
#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
|
||||||
|
|
||||||
|
#define PWR_CR1 (STM32_PWR_BASE + 0x00)
|
||||||
|
#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
|
||||||
|
#define PWR_CR1_DBP BIT(8)
|
||||||
|
#define PWR_MCUCR_SBF BIT(6)
|
||||||
|
|
||||||
|
/* GPIOZ registers */
|
||||||
|
#define GPIOZ_SECCFGR 0x54004030
|
||||||
|
|
||||||
|
/* DBGMCU register */
|
||||||
|
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
|
||||||
|
#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
|
||||||
|
#define DBGMCU_IDC_DEV_ID_SHIFT 0
|
||||||
|
#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
|
||||||
|
#define DBGMCU_IDC_REV_ID_SHIFT 16
|
||||||
|
|
||||||
|
/* boot interface from Bootrom
|
||||||
|
* - boot instance = bit 31:16
|
||||||
|
* - boot device = bit 15:0
|
||||||
|
*/
|
||||||
|
#define BOOTROM_PARAM_ADDR 0x2FFC0078
|
||||||
|
#define BOOTROM_MODE_MASK GENMASK(15, 0)
|
||||||
|
#define BOOTROM_MODE_SHIFT 0
|
||||||
|
#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
|
||||||
|
#define BOOTROM_INSTANCE_SHIFT 16
|
||||||
|
|
||||||
|
/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
|
||||||
|
#define RPN_SHIFT 0
|
||||||
|
#define RPN_MASK GENMASK(7, 0)
|
||||||
|
|
||||||
|
/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines
|
||||||
|
* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
|
||||||
|
* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
|
||||||
|
* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
|
||||||
|
* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
|
||||||
|
* - others: Reserved
|
||||||
|
*/
|
||||||
|
#define PKG_SHIFT 27
|
||||||
|
#define PKG_MASK GENMASK(2, 0)
|
||||||
|
|
||||||
|
static void security_init(void)
|
||||||
|
{
|
||||||
|
/* Disable the backup domain write protection */
|
||||||
|
/* the protection is enable at each reset by hardware */
|
||||||
|
/* And must be disable by software */
|
||||||
|
setbits_le32(PWR_CR1, PWR_CR1_DBP);
|
||||||
|
|
||||||
|
while (!(readl(PWR_CR1) & PWR_CR1_DBP))
|
||||||
|
;
|
||||||
|
|
||||||
|
/* If RTC clock isn't enable so this is a cold boot then we need
|
||||||
|
* to reset the backup domain
|
||||||
|
*/
|
||||||
|
if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
|
||||||
|
setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
||||||
|
while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
|
||||||
|
;
|
||||||
|
clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* allow non secure access in Write/Read for all peripheral */
|
||||||
|
writel(GENMASK(25, 0), ETZPC_DECPROT0);
|
||||||
|
|
||||||
|
/* Open SYSRAM for no secure access */
|
||||||
|
writel(0x0, ETZPC_TZMA1_SIZE);
|
||||||
|
|
||||||
|
/* enable TZC1 TZC2 clock */
|
||||||
|
writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
|
||||||
|
|
||||||
|
/* Region 0 set to no access by default */
|
||||||
|
/* bit 0 / 16 => nsaid0 read/write Enable
|
||||||
|
* bit 1 / 17 => nsaid1 read/write Enable
|
||||||
|
* ...
|
||||||
|
* bit 15 / 31 => nsaid15 read/write Enable
|
||||||
|
*/
|
||||||
|
writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
|
||||||
|
/* bit 30 / 31 => Secure Global Enable : write/read */
|
||||||
|
/* bit 0 / 1 => Region Enable for filter 0/1 */
|
||||||
|
writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
|
||||||
|
|
||||||
|
/* Enable Filter 0 and 1 */
|
||||||
|
setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
|
||||||
|
|
||||||
|
/* RCC trust zone deactivated */
|
||||||
|
writel(0x0, RCC_TZCR);
|
||||||
|
|
||||||
|
/* TAMP: deactivate the internal tamper
|
||||||
|
* Bit 23 ITAMP8E: monotonic counter overflow
|
||||||
|
* Bit 20 ITAMP5E: RTC calendar overflow
|
||||||
|
* Bit 19 ITAMP4E: HSE monitoring
|
||||||
|
* Bit 18 ITAMP3E: LSE monitoring
|
||||||
|
* Bit 16 ITAMP1E: RTC power domain supply monitoring
|
||||||
|
*/
|
||||||
|
writel(0x0, TAMP_CR1);
|
||||||
|
|
||||||
|
/* GPIOZ: deactivate the security */
|
||||||
|
writel(BIT(0), RCC_MP_AHB5ENSETR);
|
||||||
|
writel(0x0, GPIOZ_SECCFGR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Debug init
|
||||||
|
*/
|
||||||
|
void dbgmcu_init(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Freeze IWDG2 if Cortex-A7 is in debug mode
|
||||||
|
* done in TF-A for TRUSTED boot and
|
||||||
|
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
|
||||||
|
*/
|
||||||
|
if (bsec_dbgswenable()) {
|
||||||
|
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
||||||
|
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void spl_board_init(void)
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
dbgmcu_init();
|
||||||
|
|
||||||
|
/* force probe of BSEC driver to shadow the upper OTP */
|
||||||
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
|
||||||
|
if (ret)
|
||||||
|
log_warning("BSEC probe failed: %d\n", ret);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* get bootmode from ROM code boot context: saved in TAMP register */
|
||||||
|
static void update_bootmode(void)
|
||||||
|
{
|
||||||
|
u32 boot_mode;
|
||||||
|
u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
|
||||||
|
u32 bootrom_device, bootrom_instance;
|
||||||
|
|
||||||
|
/* enable TAMP clock = RTCAPBEN */
|
||||||
|
writel(BIT(8), RCC_MP_APB5ENSETR);
|
||||||
|
|
||||||
|
/* read bootrom context */
|
||||||
|
bootrom_device =
|
||||||
|
(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
|
||||||
|
bootrom_instance =
|
||||||
|
(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
|
||||||
|
boot_mode =
|
||||||
|
((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
|
||||||
|
((bootrom_instance << BOOT_INSTANCE_SHIFT) &
|
||||||
|
BOOT_INSTANCE_MASK);
|
||||||
|
|
||||||
|
/* save the boot mode in TAMP backup register */
|
||||||
|
clrsetbits_le32(TAMP_BOOT_CONTEXT,
|
||||||
|
TAMP_BOOT_MODE_MASK,
|
||||||
|
boot_mode << TAMP_BOOT_MODE_SHIFT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* weak function: STM32MP15x mach init for boot without TFA */
|
||||||
|
void stm32mp_cpu_init(void)
|
||||||
|
{
|
||||||
|
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||||
|
security_init();
|
||||||
|
update_bootmode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* reset copro state in SPL, when used, or in U-Boot */
|
||||||
|
if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||||
|
/* Reset Coprocessor state unless it wakes up from Standby power mode */
|
||||||
|
if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
|
||||||
|
writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
|
||||||
|
writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 read_idc(void)
|
||||||
|
{
|
||||||
|
/* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
|
||||||
|
if (bsec_dbgswenable()) {
|
||||||
|
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
||||||
|
|
||||||
|
return readl(DBGMCU_IDC);
|
||||||
|
}
|
||||||
|
|
||||||
|
return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_cpu_dev(void)
|
||||||
|
{
|
||||||
|
return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_cpu_rev(void)
|
||||||
|
{
|
||||||
|
return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get Device Part Number (RPN) from OTP */
|
||||||
|
static u32 get_cpu_rpn(void)
|
||||||
|
{
|
||||||
|
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_cpu_type(void)
|
||||||
|
{
|
||||||
|
return (get_cpu_dev() << 16) | get_cpu_rpn();
|
||||||
|
}
|
||||||
|
|
||||||
|
int get_eth_nb(void)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get Package options from OTP */
|
||||||
|
u32 get_cpu_package(void)
|
||||||
|
{
|
||||||
|
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char * const soc_type[] = {
|
||||||
|
"????",
|
||||||
|
"151C", "151A", "151F", "151D",
|
||||||
|
"153C", "153A", "153F", "153D",
|
||||||
|
"157C", "157A", "157F", "157D"
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
|
||||||
|
static const char * const soc_rev[] = { "?", "A", "B", "Z" };
|
||||||
|
|
||||||
|
static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
|
||||||
|
unsigned int *rev)
|
||||||
|
{
|
||||||
|
u32 cpu_type = get_cpu_type();
|
||||||
|
u32 ct = cpu_type & ~(BIT(7) | BIT(0));
|
||||||
|
u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
|
||||||
|
u32 cp = get_cpu_package();
|
||||||
|
|
||||||
|
/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
|
||||||
|
switch (ct) {
|
||||||
|
case CPU_STM32MP151Cxx:
|
||||||
|
*type = cm + 1;
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP153Cxx:
|
||||||
|
*type = cm + 5;
|
||||||
|
break;
|
||||||
|
case CPU_STM32MP157Cxx:
|
||||||
|
*type = cm + 9;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
*type = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Package */
|
||||||
|
switch (cp) {
|
||||||
|
case STM32MP15_PKG_AA_LBGA448:
|
||||||
|
case STM32MP15_PKG_AB_LBGA354:
|
||||||
|
case STM32MP15_PKG_AC_TFBGA361:
|
||||||
|
case STM32MP15_PKG_AD_TFBGA257:
|
||||||
|
*pkg = cp;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
*pkg = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Revision */
|
||||||
|
switch (get_cpu_rev()) {
|
||||||
|
case CPU_REV1:
|
||||||
|
*rev = 1;
|
||||||
|
break;
|
||||||
|
case CPU_REV2:
|
||||||
|
*rev = 2;
|
||||||
|
break;
|
||||||
|
case CPU_REV2_1:
|
||||||
|
*rev = 3;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
*rev = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void get_soc_name(char name[SOC_NAME_SIZE])
|
||||||
|
{
|
||||||
|
unsigned int type, pkg, rev;
|
||||||
|
|
||||||
|
get_cpu_string_offsets(&type, &pkg, &rev);
|
||||||
|
|
||||||
|
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
|
||||||
|
soc_type[type], soc_pkg[pkg], soc_rev[rev]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_soc_type_pkg_rev(void)
|
||||||
|
{
|
||||||
|
unsigned int type, pkg, rev;
|
||||||
|
|
||||||
|
get_cpu_string_offsets(&type, &pkg, &rev);
|
||||||
|
|
||||||
|
env_set("soc_type", soc_type[type]);
|
||||||
|
env_set("soc_pkg", soc_pkg[pkg]);
|
||||||
|
env_set("soc_rev", soc_rev[rev]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* weak function called in arch_misc_init */
|
||||||
|
void stm32mp_misc_init(void)
|
||||||
|
{
|
||||||
|
setup_soc_type_pkg_rev();
|
||||||
|
}
|
||||||
@ -9,7 +9,6 @@
|
|||||||
#include <net.h>
|
#include <net.h>
|
||||||
#include <asm/arch/stm32.h>
|
#include <asm/arch/stm32.h>
|
||||||
#include <asm/arch/sys_proto.h>
|
#include <asm/arch/sys_proto.h>
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/gpio.h>
|
#include <asm/gpio.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <bootm.h>
|
#include <bootm.h>
|
||||||
@ -78,11 +77,6 @@
|
|||||||
#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
|
#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
|
||||||
#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
|
#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
|
||||||
|
|
||||||
/*
|
|
||||||
* Get a global data pointer
|
|
||||||
*/
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#define KS_CCR 0x08
|
#define KS_CCR 0x08
|
||||||
#define KS_CCR_EEPROM BIT(9)
|
#define KS_CCR_EEPROM BIT(9)
|
||||||
#define KS_BE0 BIT(12)
|
#define KS_BE0 BIT(12)
|
||||||
@ -96,14 +90,15 @@ int setup_mac_address(void)
|
|||||||
bool skip_eth0 = false;
|
bool skip_eth0 = false;
|
||||||
bool skip_eth1 = false;
|
bool skip_eth1 = false;
|
||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
int off, ret;
|
int ret;
|
||||||
|
ofnode node;
|
||||||
|
|
||||||
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
|
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
|
||||||
if (ret) /* ethaddr is already set */
|
if (ret) /* ethaddr is already set */
|
||||||
skip_eth0 = true;
|
skip_eth0 = true;
|
||||||
|
|
||||||
off = fdt_path_offset(gd->fdt_blob, "ethernet1");
|
node = ofnode_path("ethernet1");
|
||||||
if (off < 0) {
|
if (!ofnode_valid(node)) {
|
||||||
/* ethernet1 is not present in the system */
|
/* ethernet1 is not present in the system */
|
||||||
skip_eth1 = true;
|
skip_eth1 = true;
|
||||||
goto out_set_ethaddr;
|
goto out_set_ethaddr;
|
||||||
@ -116,7 +111,7 @@ int setup_mac_address(void)
|
|||||||
goto out_set_ethaddr;
|
goto out_set_ethaddr;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
|
ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll");
|
||||||
if (ret)
|
if (ret)
|
||||||
goto out_set_ethaddr;
|
goto out_set_ethaddr;
|
||||||
|
|
||||||
@ -127,7 +122,7 @@ int setup_mac_address(void)
|
|||||||
* MAC address.
|
* MAC address.
|
||||||
*/
|
*/
|
||||||
u32 reg, cider, ccr;
|
u32 reg, cider, ccr;
|
||||||
reg = fdt_get_base_address(gd->fdt_blob, off);
|
reg = ofnode_get_addr(node);
|
||||||
if (!reg)
|
if (!reg)
|
||||||
goto out_set_ethaddr;
|
goto out_set_ethaddr;
|
||||||
|
|
||||||
@ -149,13 +144,13 @@ out_set_ethaddr:
|
|||||||
if (skip_eth0 && skip_eth1)
|
if (skip_eth0 && skip_eth1)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
|
node = ofnode_path("eeprom0");
|
||||||
if (off < 0) {
|
if (!ofnode_valid(node)) {
|
||||||
printf("%s: No eeprom0 path offset\n", __func__);
|
printf("%s: No eeprom0 path offset\n", __func__);
|
||||||
return off;
|
return -ENOENT;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
|
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
printf("Cannot find EEPROM!\n");
|
printf("Cannot find EEPROM!\n");
|
||||||
return ret;
|
return ret;
|
||||||
@ -191,7 +186,7 @@ int checkboard(void)
|
|||||||
mode = "basic";
|
mode = "basic";
|
||||||
|
|
||||||
printf("Board: stm32mp1 in %s mode", mode);
|
printf("Board: stm32mp1 in %s mode", mode);
|
||||||
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
|
||||||
&fdt_compat_len);
|
&fdt_compat_len);
|
||||||
if (fdt_compat && fdt_compat_len)
|
if (fdt_compat && fdt_compat_len)
|
||||||
printf(" (%s)", fdt_compat);
|
printf(" (%s)", fdt_compat);
|
||||||
@ -289,7 +284,7 @@ int board_fit_config_name_match(const char *name)
|
|||||||
const char *compat;
|
const char *compat;
|
||||||
char test[128];
|
char test[128];
|
||||||
|
|
||||||
compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
|
compat = ofnode_get_property(ofnode_root(), "compatible", NULL);
|
||||||
|
|
||||||
snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
|
snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
|
||||||
compat, somcode, brdcode);
|
compat, somcode, brdcode);
|
||||||
@ -604,14 +599,13 @@ static void board_init_fmc2(void)
|
|||||||
#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) ((((n) - 1) & 3) * 2)
|
#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) ((((n) - 1) & 3) * 2)
|
||||||
static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
|
static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
|
||||||
{
|
{
|
||||||
const void *fdt = gd->fdt_blob;
|
|
||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
u8 bucks_vout = 0;
|
u8 bucks_vout = 0;
|
||||||
const char *prop;
|
const char *prop;
|
||||||
int len, ret;
|
int len, ret;
|
||||||
|
|
||||||
/* Check whether this is Avenger96 board. */
|
/* Check whether this is Avenger96 board. */
|
||||||
prop = fdt_getprop(fdt, 0, "compatible", &len);
|
prop = ofnode_get_property(ofnode_root(), "compatible", &len);
|
||||||
if (!prop || !len)
|
if (!prop || !len)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
|
|
||||||
@ -701,7 +695,7 @@ int board_late_init(void)
|
|||||||
const void *fdt_compat;
|
const void *fdt_compat;
|
||||||
int fdt_compat_len;
|
int fdt_compat_len;
|
||||||
|
|
||||||
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
|
||||||
&fdt_compat_len);
|
&fdt_compat_len);
|
||||||
if (fdt_compat && fdt_compat_len) {
|
if (fdt_compat && fdt_compat_len) {
|
||||||
if (strncmp(fdt_compat, "st,", 3) != 0)
|
if (strncmp(fdt_compat, "st,", 3) != 0)
|
||||||
|
|||||||
@ -14,8 +14,6 @@
|
|||||||
#include <asm/arch/sys_proto.h>
|
#include <asm/arch/sys_proto.h>
|
||||||
#include <power/regulator.h>
|
#include <power/regulator.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
int checkboard(void)
|
int checkboard(void)
|
||||||
{
|
{
|
||||||
char *mode;
|
char *mode;
|
||||||
@ -28,7 +26,7 @@ int checkboard(void)
|
|||||||
mode = "basic";
|
mode = "basic";
|
||||||
|
|
||||||
printf("Board: stm32mp1 in %s mode", mode);
|
printf("Board: stm32mp1 in %s mode", mode);
|
||||||
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
|
||||||
&fdt_compat_len);
|
&fdt_compat_len);
|
||||||
if (fdt_compat && fdt_compat_len)
|
if (fdt_compat && fdt_compat_len)
|
||||||
printf(" (%s)", fdt_compat);
|
printf(" (%s)", fdt_compat);
|
||||||
|
|||||||
@ -202,18 +202,4 @@ void stpmic1_init(u32 voltage_mv)
|
|||||||
STPMIC1_BUCKS_MRST_CR,
|
STPMIC1_BUCKS_MRST_CR,
|
||||||
STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
|
STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
|
||||||
STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
|
STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
|
||||||
|
|
||||||
/* Check if debug is enabled to program PMIC according to the bit */
|
|
||||||
if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
|
|
||||||
log_info("Keep debug unit ON\n");
|
|
||||||
|
|
||||||
pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
|
|
||||||
STPMIC1_MRST_BUCK_DEBUG,
|
|
||||||
STPMIC1_MRST_BUCK_DEBUG);
|
|
||||||
|
|
||||||
if (STPMIC1_MRST_LDO_DEBUG)
|
|
||||||
pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
|
|
||||||
STPMIC1_MRST_LDO_DEBUG,
|
|
||||||
STPMIC1_MRST_LDO_DEBUG);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|||||||
@ -11,3 +11,18 @@ config SYS_CONFIG_NAME
|
|||||||
|
|
||||||
source "board/st/common/Kconfig"
|
source "board/st/common/Kconfig"
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
if TARGET_ST_STM32MP13x
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "stm32mp1"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "st"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "stm32mp13_st_common"
|
||||||
|
|
||||||
|
source "board/st/common/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
|
|||||||
@ -3,10 +3,14 @@ M: Patrick Delaunay <patrick.delaunay@foss.st.com>
|
|||||||
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
||||||
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
|
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
|
||||||
S: Maintained
|
S: Maintained
|
||||||
|
F: arch/arm/dts/stm32mp13*
|
||||||
F: arch/arm/dts/stm32mp15*
|
F: arch/arm/dts/stm32mp15*
|
||||||
F: board/st/stm32mp1/
|
F: board/st/stm32mp1/
|
||||||
|
F: configs/stm32mp13_defconfig
|
||||||
F: configs/stm32mp15_defconfig
|
F: configs/stm32mp15_defconfig
|
||||||
F: configs/stm32mp15_basic_defconfig
|
F: configs/stm32mp15_basic_defconfig
|
||||||
F: configs/stm32mp15_trusted_defconfig
|
F: configs/stm32mp15_trusted_defconfig
|
||||||
|
F: include/configs/stm32mp13_common.h
|
||||||
|
F: include/configs/stm32mp13_st_common.h
|
||||||
F: include/configs/stm32mp15_common.h
|
F: include/configs/stm32mp15_common.h
|
||||||
F: include/configs/stm32mp15_st_common.h
|
F: include/configs/stm32mp15_st_common.h
|
||||||
|
|||||||
@ -82,11 +82,6 @@
|
|||||||
#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
|
#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
|
||||||
#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
|
#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
|
||||||
|
|
||||||
/*
|
|
||||||
* Get a global data pointer
|
|
||||||
*/
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#define USB_LOW_THRESHOLD_UV 200000
|
#define USB_LOW_THRESHOLD_UV 200000
|
||||||
#define USB_WARNING_LOW_THRESHOLD_UV 660000
|
#define USB_WARNING_LOW_THRESHOLD_UV 660000
|
||||||
#define USB_START_LOW_THRESHOLD_UV 1230000
|
#define USB_START_LOW_THRESHOLD_UV 1230000
|
||||||
@ -116,7 +111,7 @@ int checkboard(void)
|
|||||||
mode = "basic";
|
mode = "basic";
|
||||||
}
|
}
|
||||||
|
|
||||||
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
|
||||||
&fdt_compat_len);
|
&fdt_compat_len);
|
||||||
|
|
||||||
log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
|
log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
|
||||||
@ -554,8 +549,7 @@ static void sysconf_init(void)
|
|||||||
clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
|
clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
|
static int board_stm32mp15x_dk2_init(void)
|
||||||
static int dk2_i2c1_fix(void)
|
|
||||||
{
|
{
|
||||||
ofnode node;
|
ofnode node;
|
||||||
struct gpio_desc hdmi, audio;
|
struct gpio_desc hdmi, audio;
|
||||||
@ -564,6 +558,7 @@ static int dk2_i2c1_fix(void)
|
|||||||
if (!IS_ENABLED(CONFIG_DM_REGULATOR))
|
if (!IS_ENABLED(CONFIG_DM_REGULATOR))
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
|
|
||||||
|
/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
|
||||||
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
|
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
|
||||||
if (!ofnode_valid(node)) {
|
if (!ofnode_valid(node)) {
|
||||||
log_debug("no hdmi-transmitter@39 ?\n");
|
log_debug("no hdmi-transmitter@39 ?\n");
|
||||||
@ -611,7 +606,7 @@ error:
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool board_is_dk2(void)
|
static bool board_is_stm32mp15x_dk2(void)
|
||||||
{
|
{
|
||||||
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
|
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
|
||||||
of_machine_is_compatible("st,stm32mp157c-dk2"))
|
of_machine_is_compatible("st,stm32mp157c-dk2"))
|
||||||
@ -620,7 +615,7 @@ static bool board_is_dk2(void)
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool board_is_ev1(void)
|
static bool board_is_stm32mp15x_ev1(void)
|
||||||
{
|
{
|
||||||
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
|
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
|
||||||
(of_machine_is_compatible("st,stm32mp157a-ev1") ||
|
(of_machine_is_compatible("st,stm32mp157a-ev1") ||
|
||||||
@ -644,7 +639,7 @@ U_BOOT_DRIVER(goodix) = {
|
|||||||
.of_match = goodix_ids,
|
.of_match = goodix_ids,
|
||||||
};
|
};
|
||||||
|
|
||||||
static void board_ev1_init(void)
|
static void board_stm32mp15x_ev1_init(void)
|
||||||
{
|
{
|
||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
|
|
||||||
@ -657,11 +652,11 @@ int board_init(void)
|
|||||||
{
|
{
|
||||||
board_key_check();
|
board_key_check();
|
||||||
|
|
||||||
if (board_is_ev1())
|
if (board_is_stm32mp15x_ev1())
|
||||||
board_ev1_init();
|
board_stm32mp15x_ev1_init();
|
||||||
|
|
||||||
if (board_is_dk2())
|
if (board_is_stm32mp15x_dk2())
|
||||||
dk2_i2c1_fix();
|
board_stm32mp15x_dk2_init();
|
||||||
|
|
||||||
if (IS_ENABLED(CONFIG_DM_REGULATOR))
|
if (IS_ENABLED(CONFIG_DM_REGULATOR))
|
||||||
regulators_enable_boot_on(_DEBUG);
|
regulators_enable_boot_on(_DEBUG);
|
||||||
@ -690,7 +685,7 @@ int board_late_init(void)
|
|||||||
int buf_len;
|
int buf_len;
|
||||||
|
|
||||||
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
|
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
|
||||||
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
|
||||||
&fdt_compat_len);
|
&fdt_compat_len);
|
||||||
if (fdt_compat && fdt_compat_len) {
|
if (fdt_compat && fdt_compat_len) {
|
||||||
if (strncmp(fdt_compat, "st,", 3) != 0) {
|
if (strncmp(fdt_compat, "st,", 3) != 0) {
|
||||||
|
|||||||
55
configs/stm32mp13_defconfig
Normal file
55
configs/stm32mp13_defconfig
Normal file
@ -0,0 +1,55 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_STM32MP=y
|
||||||
|
CONFIG_TFABOOT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x180000
|
||||||
|
CONFIG_ENV_OFFSET=0x900000
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk"
|
||||||
|
CONFIG_STM32MP13x=y
|
||||||
|
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
||||||
|
CONFIG_TARGET_ST_STM32MP13x=y
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x940000
|
||||||
|
# CONFIG_ARMV7_NONSEC is not set
|
||||||
|
CONFIG_SYS_LOAD_ADDR=0xc2000000
|
||||||
|
CONFIG_SYS_MEMTEST_START=0xc0000000
|
||||||
|
CONFIG_SYS_MEMTEST_END=0xc4000000
|
||||||
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
|
||||||
|
CONFIG_FIT=y
|
||||||
|
CONFIG_BOOTDELAY=1
|
||||||
|
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
|
||||||
|
CONFIG_SYS_PROMPT="STM32MP> "
|
||||||
|
CONFIG_CMD_ADTIMG=y
|
||||||
|
CONFIG_CMD_ERASEENV=y
|
||||||
|
CONFIG_CMD_MEMINFO=y
|
||||||
|
CONFIG_CMD_MEMTEST=y
|
||||||
|
CONFIG_CMD_CLK=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_TIMER=y
|
||||||
|
CONFIG_CMD_LOG=y
|
||||||
|
CONFIG_OF_LIVE=y
|
||||||
|
CONFIG_ENV_IS_NOWHERE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_SYS_MMC_ENV_DEV=-1
|
||||||
|
CONFIG_CLK_SCMI=y
|
||||||
|
CONFIG_STM32_SDMMC2=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_PINCONF=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_DM_REGULATOR_SCMI=y
|
||||||
|
CONFIG_RESET_SCMI=y
|
||||||
|
CONFIG_SERIAL_RX_BUFFER=y
|
||||||
|
CONFIG_SYSRESET_PSCI=y
|
||||||
|
CONFIG_TEE=y
|
||||||
|
CONFIG_OPTEE=y
|
||||||
|
# CONFIG_OPTEE_TA_AVB is not set
|
||||||
|
CONFIG_ERRNO_STR=y
|
||||||
|
# CONFIG_LMB_USE_MAX_REGIONS is not set
|
||||||
|
CONFIG_LMB_MEMORY_REGIONS=2
|
||||||
|
CONFIG_LMB_RESERVED_REGIONS=16
|
||||||
@ -8,11 +8,11 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
|
|||||||
CONFIG_SPL_TEXT_BASE=0x2FFC2500
|
CONFIG_SPL_TEXT_BASE=0x2FFC2500
|
||||||
CONFIG_SPL_MMC=y
|
CONFIG_SPL_MMC=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_TARGET_ST_STM32MP15x=y
|
|
||||||
CONFIG_CMD_STM32KEY=y
|
CONFIG_CMD_STM32KEY=y
|
||||||
CONFIG_CMD_STM32PROG=y
|
|
||||||
CONFIG_ENV_OFFSET_REDUND=0x2C0000
|
|
||||||
CONFIG_TYPEC_STUSB160X=y
|
CONFIG_TYPEC_STUSB160X=y
|
||||||
|
CONFIG_TARGET_ST_STM32MP15x=y
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x2C0000
|
||||||
|
CONFIG_CMD_STM32PROG=y
|
||||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||||
CONFIG_SPL_SPI=y
|
CONFIG_SPL_SPI=y
|
||||||
# CONFIG_ARMV7_VIRT is not set
|
# CONFIG_ARMV7_VIRT is not set
|
||||||
|
|||||||
@ -5,12 +5,12 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000
|
|||||||
CONFIG_ENV_OFFSET=0x480000
|
CONFIG_ENV_OFFSET=0x480000
|
||||||
CONFIG_ENV_SECT_SIZE=0x40000
|
CONFIG_ENV_SECT_SIZE=0x40000
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
|
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
|
||||||
CONFIG_TARGET_ST_STM32MP15x=y
|
|
||||||
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
||||||
CONFIG_CMD_STM32KEY=y
|
CONFIG_CMD_STM32KEY=y
|
||||||
CONFIG_CMD_STM32PROG=y
|
|
||||||
CONFIG_ENV_OFFSET_REDUND=0x4C0000
|
|
||||||
CONFIG_TYPEC_STUSB160X=y
|
CONFIG_TYPEC_STUSB160X=y
|
||||||
|
CONFIG_TARGET_ST_STM32MP15x=y
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x4C0000
|
||||||
|
CONFIG_CMD_STM32PROG=y
|
||||||
# CONFIG_ARMV7_NONSEC is not set
|
# CONFIG_ARMV7_NONSEC is not set
|
||||||
CONFIG_SYS_LOAD_ADDR=0xc2000000
|
CONFIG_SYS_LOAD_ADDR=0xc2000000
|
||||||
CONFIG_SYS_MEMTEST_START=0xc0000000
|
CONFIG_SYS_MEMTEST_START=0xc0000000
|
||||||
|
|||||||
@ -84,6 +84,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(
|
|||||||
# CONFIG_SPL_DOS_PARTITION is not set
|
# CONFIG_SPL_DOS_PARTITION is not set
|
||||||
# CONFIG_ISO_PARTITION is not set
|
# CONFIG_ISO_PARTITION is not set
|
||||||
# CONFIG_SPL_PARTITION_UUIDS is not set
|
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||||
|
CONFIG_OF_LIVE=y
|
||||||
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
|
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
|
||||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
|
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
|
||||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||||
|
|||||||
@ -82,6 +82,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(
|
|||||||
# CONFIG_SPL_DOS_PARTITION is not set
|
# CONFIG_SPL_DOS_PARTITION is not set
|
||||||
# CONFIG_ISO_PARTITION is not set
|
# CONFIG_ISO_PARTITION is not set
|
||||||
# CONFIG_SPL_PARTITION_UUIDS is not set
|
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||||
|
CONFIG_OF_LIVE=y
|
||||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
|
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
|
||||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||||
|
|||||||
@ -5,13 +5,13 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000
|
|||||||
CONFIG_ENV_OFFSET=0x280000
|
CONFIG_ENV_OFFSET=0x280000
|
||||||
CONFIG_ENV_SECT_SIZE=0x40000
|
CONFIG_ENV_SECT_SIZE=0x40000
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
|
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
|
||||||
CONFIG_STM32MP15x_STM32IMAGE=y
|
|
||||||
CONFIG_TARGET_ST_STM32MP15x=y
|
|
||||||
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
|
||||||
CONFIG_CMD_STM32KEY=y
|
CONFIG_CMD_STM32KEY=y
|
||||||
CONFIG_CMD_STM32PROG=y
|
|
||||||
CONFIG_ENV_OFFSET_REDUND=0x2C0000
|
|
||||||
CONFIG_TYPEC_STUSB160X=y
|
CONFIG_TYPEC_STUSB160X=y
|
||||||
|
CONFIG_STM32MP15x_STM32IMAGE=y
|
||||||
|
CONFIG_TARGET_ST_STM32MP15x=y
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x2C0000
|
||||||
|
CONFIG_CMD_STM32PROG=y
|
||||||
# CONFIG_ARMV7_NONSEC is not set
|
# CONFIG_ARMV7_NONSEC is not set
|
||||||
CONFIG_SYS_LOAD_ADDR=0xc2000000
|
CONFIG_SYS_LOAD_ADDR=0xc2000000
|
||||||
CONFIG_SYS_MEMTEST_START=0xc0000000
|
CONFIG_SYS_MEMTEST_START=0xc0000000
|
||||||
|
|||||||
@ -1,41 +1,31 @@
|
|||||||
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||||
.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
|
.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
|
||||||
|
|
||||||
STM32MP15x boards
|
STM32MP1xx boards
|
||||||
=================
|
=================
|
||||||
|
|
||||||
This is a quick instruction for setup STM32MP15x boards.
|
This is a quick instruction for setup STMicroelectronics STM32MP1xx boards.
|
||||||
|
|
||||||
Futher information can be found in STMicrolectronics STM32 WIKI_.
|
Further information can be found in STMicroelectronics STM32 WIKI_.
|
||||||
|
|
||||||
Supported devices
|
Supported devices
|
||||||
-----------------
|
-----------------
|
||||||
|
|
||||||
U-Boot supports STMP32MP15x SoCs:
|
U-Boot supports all the STMicroelectronics MPU with the associated boards
|
||||||
|
|
||||||
|
- STMP32MP15x SoCs:
|
||||||
|
|
||||||
- STM32MP157
|
- STM32MP157
|
||||||
- STM32MP153
|
- STM32MP153
|
||||||
- STM32MP151
|
- STM32MP151
|
||||||
|
|
||||||
The STM32MP15x is a Cortex-A MPU aimed at various applications.
|
- STMP32MP13x SoCs:
|
||||||
|
|
||||||
It features:
|
- STM32MP135
|
||||||
|
- STM32MP133
|
||||||
|
- STM32MP131
|
||||||
|
|
||||||
- Dual core Cortex-A7 application core (Single on STM32MP151)
|
Everything is supported in Linux but U-Boot is limited to the boot device:
|
||||||
- 2D/3D image composition with GPU (only on STM32MP157)
|
|
||||||
- Standard memories interface support
|
|
||||||
- Standard connectivity, widely inherited from the STM32 MCU family
|
|
||||||
- Comprehensive security support
|
|
||||||
|
|
||||||
Each line comes with a security option (cryptography & secure boot) and
|
|
||||||
a Cortex-A frequency option:
|
|
||||||
|
|
||||||
- A : Cortex-A7 @ 650 MHz
|
|
||||||
- C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
|
|
||||||
- D : Cortex-A7 @ 800 MHz
|
|
||||||
- F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
|
|
||||||
|
|
||||||
Everything is supported in Linux but U-Boot is limited to:
|
|
||||||
|
|
||||||
1. UART
|
1. UART
|
||||||
2. SD card/MMC controller (SDMMC)
|
2. SD card/MMC controller (SDMMC)
|
||||||
@ -49,7 +39,35 @@ And the necessary drivers
|
|||||||
1. I2C
|
1. I2C
|
||||||
2. STPMIC1 (PMIC and regulator)
|
2. STPMIC1 (PMIC and regulator)
|
||||||
3. Clock, Reset, Sysreset
|
3. Clock, Reset, Sysreset
|
||||||
4. Fuse
|
4. Fuse (BSEC)
|
||||||
|
5. OP-TEE
|
||||||
|
6. ETH
|
||||||
|
7. USB host
|
||||||
|
8. WATCHDOG
|
||||||
|
9. RNG
|
||||||
|
10. RTC
|
||||||
|
|
||||||
|
STM32MP15x
|
||||||
|
``````````
|
||||||
|
|
||||||
|
The STM32MP15x is a Cortex-A7 MPU aimed at various applications.
|
||||||
|
|
||||||
|
It features:
|
||||||
|
|
||||||
|
- Dual core Cortex-A7 application core (Single on STM32MP151)
|
||||||
|
- 2D/3D image composition with GPU (only on STM32MP157)
|
||||||
|
- Standard memories interface support
|
||||||
|
- Standard connectivity, widely inherited from the STM32 MCU family
|
||||||
|
- Comprehensive security support
|
||||||
|
- Cortex M4 coprocessor
|
||||||
|
|
||||||
|
Each line comes with a security option (cryptography & secure boot) and
|
||||||
|
a Cortex-A frequency option:
|
||||||
|
|
||||||
|
- A : Cortex-A7 @ 650 MHz
|
||||||
|
- C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
|
||||||
|
- D : Cortex-A7 @ 800 MHz
|
||||||
|
- F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
|
||||||
|
|
||||||
Currently the following boards are supported:
|
Currently the following boards are supported:
|
||||||
|
|
||||||
@ -59,6 +77,16 @@ Currently the following boards are supported:
|
|||||||
+ stm32mp157c-ev1.dts
|
+ stm32mp157c-ev1.dts
|
||||||
+ stm32mp15xx-dhcor-avenger96.dts
|
+ stm32mp15xx-dhcor-avenger96.dts
|
||||||
|
|
||||||
|
STM32MP13x
|
||||||
|
``````````
|
||||||
|
|
||||||
|
The STM32MP13x is a single Cortex-A7 MPU aimed at various applications.
|
||||||
|
|
||||||
|
Currently the following boards are supported:
|
||||||
|
|
||||||
|
+ stm32mp135f-dk.dts
|
||||||
|
|
||||||
|
|
||||||
Boot Sequences
|
Boot Sequences
|
||||||
--------------
|
--------------
|
||||||
|
|
||||||
@ -71,12 +99,22 @@ Boot Sequences
|
|||||||
+ +------------------------+-------------------------+--------------+
|
+ +------------------------+-------------------------+--------------+
|
||||||
| | embedded RAM | DDR |
|
| | embedded RAM | DDR |
|
||||||
+----------+------------------------+-------------------------+--------------+
|
+----------+------------------------+-------------------------+--------------+
|
||||||
|
| TrustZone| secure monitor |
|
||||||
|
+----------+------------------------+-------------------------+--------------+
|
||||||
|
|
||||||
|
The trusted boot chain is recommended with:
|
||||||
|
|
||||||
|
- FSBL = **TF-A BL2**
|
||||||
|
- Secure monitor = **OP-TEE**
|
||||||
|
- SSBL = **U-Boot**
|
||||||
|
|
||||||
|
It is the only supported boot chain for STM32MP13x family.
|
||||||
|
|
||||||
The **Trusted** boot chain with TF-A_
|
The **Trusted** boot chain with TF-A_
|
||||||
`````````````````````````````````````
|
`````````````````````````````````````
|
||||||
|
|
||||||
defconfig_file :
|
defconfig_file :
|
||||||
+ **stm32mp15_defconfig** (for TF-A_ with FIP support)
|
+ **stm32mp15_defconfig** and **stm32mp13_defconfig** (for TF-A_ with FIP support)
|
||||||
+ **stm32mp15_trusted_defconfig** (for TF-A_ without FIP support)
|
+ **stm32mp15_trusted_defconfig** (for TF-A_ without FIP support)
|
||||||
|
|
||||||
+-------------+--------------------------+------------+-------+
|
+-------------+--------------------------+------------+-------+
|
||||||
@ -98,8 +136,8 @@ TF-A_ (BL2) initialize the DDR and loads the next stage binaries from a FIP file
|
|||||||
the secure monitor to access to secure resources.
|
the secure monitor to access to secure resources.
|
||||||
+ HW_CONFIG: The hardware configuration file = the U-Boot device tree
|
+ HW_CONFIG: The hardware configuration file = the U-Boot device tree
|
||||||
|
|
||||||
The **Basic** boot chain with SPL
|
The **Basic** boot chain with SPL (for STM32MP15x)
|
||||||
`````````````````````````````````
|
``````````````````````````````````````````````````
|
||||||
|
|
||||||
defconfig_file :
|
defconfig_file :
|
||||||
+ **stm32mp15_basic_defconfig**
|
+ **stm32mp15_basic_defconfig**
|
||||||
@ -117,16 +155,19 @@ SPL has limited security initialization.
|
|||||||
U-Boot is running in secure mode and provide a secure monitor to the kernel
|
U-Boot is running in secure mode and provide a secure monitor to the kernel
|
||||||
with only PSCI support (Power State Coordination Interface defined by ARM).
|
with only PSCI support (Power State Coordination Interface defined by ARM).
|
||||||
|
|
||||||
All the STM32MP15x boards supported by U-Boot use the same generic board
|
.. warning:: This alternate **basic** boot chain with SPL is not supported/promoted by STMicroelectronics to make product.
|
||||||
stm32mp1 which support all the bootable devices.
|
|
||||||
|
|
||||||
Each board is configured only with the associated device tree.
|
Device Tree
|
||||||
|
-----------
|
||||||
|
|
||||||
Device Tree Selection
|
All the STM32MP15x and STM32MP13x boards supported by U-Boot use the same generic board
|
||||||
---------------------
|
stm32mp1 which supports all the bootable devices.
|
||||||
|
|
||||||
You need to select the appropriate device tree for your board,
|
Each STMicroelectronics board is only configured with the associated device tree.
|
||||||
the supported device trees for STM32MP15x are:
|
|
||||||
|
STM32MP15x device Tree Selection
|
||||||
|
````````````````````````````````
|
||||||
|
The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig) are:
|
||||||
|
|
||||||
+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
|
+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
|
||||||
|
|
||||||
@ -148,6 +189,15 @@ the supported device trees for STM32MP15x are:
|
|||||||
|
|
||||||
+ stm32mp15xx-dhcor-avenger96
|
+ stm32mp15xx-dhcor-avenger96
|
||||||
|
|
||||||
|
STM32MP13x device Tree Selection
|
||||||
|
````````````````````````````````
|
||||||
|
The supported device trees for STM32MP13x (stm32mp13_defconfig) are:
|
||||||
|
|
||||||
|
+ dk: Discovery board
|
||||||
|
|
||||||
|
+ stm32mp135f-dk
|
||||||
|
|
||||||
|
|
||||||
Build Procedure
|
Build Procedure
|
||||||
---------------
|
---------------
|
||||||
|
|
||||||
@ -170,6 +220,7 @@ Build Procedure
|
|||||||
|
|
||||||
for example: use one output directory for each configuration::
|
for example: use one output directory for each configuration::
|
||||||
|
|
||||||
|
# export KBUILD_OUTPUT=stm32mp13
|
||||||
# export KBUILD_OUTPUT=stm32mp15
|
# export KBUILD_OUTPUT=stm32mp15
|
||||||
# export KBUILD_OUTPUT=stm32mp15_trusted
|
# export KBUILD_OUTPUT=stm32mp15_trusted
|
||||||
# export KBUILD_OUTPUT=stm32mp15_basic
|
# export KBUILD_OUTPUT=stm32mp15_basic
|
||||||
@ -184,9 +235,10 @@ Build Procedure
|
|||||||
|
|
||||||
with <defconfig_file>:
|
with <defconfig_file>:
|
||||||
|
|
||||||
- For **trusted** boot mode : **stm32mp15_defconfig** or
|
- For **trusted** boot mode :
|
||||||
stm32mp15_trusted_defconfig
|
- For STM32MP13x: **stm32mp13_defconfig**
|
||||||
- For basic boot mode: stm32mp15_basic_defconfig
|
- For STM32MP15x: **stm32mp15_defconfig** or stm32mp15_trusted_defconfig
|
||||||
|
- For STM32MP15x basic boot mode: stm32mp15_basic_defconfig
|
||||||
|
|
||||||
5. Configure the device-tree and build the U-Boot image::
|
5. Configure the device-tree and build the U-Boot image::
|
||||||
|
|
||||||
@ -194,37 +246,42 @@ Build Procedure
|
|||||||
|
|
||||||
Examples:
|
Examples:
|
||||||
|
|
||||||
a) trusted boot with FIP on ev1::
|
a) trusted boot with FIP on STM32MP15x ev1::
|
||||||
|
|
||||||
# export KBUILD_OUTPUT=stm32mp15
|
# export KBUILD_OUTPUT=stm32mp15
|
||||||
# make stm32mp15_defconfig
|
# make stm32mp15_defconfig
|
||||||
# make DEVICE_TREE=stm32mp157c-ev1 all
|
# make DEVICE_TREE=stm32mp157c-ev1 all
|
||||||
|
|
||||||
b) trusted boot without FIP on dk2::
|
b) trusted boot on STM32MP13x discovery board::
|
||||||
|
|
||||||
# export KBUILD_OUTPUT=stm32mp15_trusted
|
# export KBUILD_OUTPUT=stm32mp13
|
||||||
# make stm32mp15_trusted_defconfig
|
# make stm32mp13_defconfig
|
||||||
# make DEVICE_TREE=stm32mp157c-dk2 all
|
# make DEVICE_TREE=stm32mp135f-dk all
|
||||||
|
|
||||||
c) basic boot on ev1::
|
DEVICE_TEE selection is optional as stm32mp135f-dk is the default board of the defconfig::
|
||||||
|
|
||||||
|
# make stm32mp13_defconfig
|
||||||
|
# make all
|
||||||
|
|
||||||
|
c) basic boot on STM32MP15x ev1::
|
||||||
|
|
||||||
# export KBUILD_OUTPUT=stm32mp15_basic
|
# export KBUILD_OUTPUT=stm32mp15_basic
|
||||||
# make stm32mp15_basic_defconfig
|
# make stm32mp15_basic_defconfig
|
||||||
# make DEVICE_TREE=stm32mp157c-ev1 all
|
# make DEVICE_TREE=stm32mp157c-ev1 all
|
||||||
|
|
||||||
d) basic boot on ed1::
|
d) basic boot on STM32MP15x ed1::
|
||||||
|
|
||||||
# export KBUILD_OUTPUT=stm32mp15_basic
|
# export KBUILD_OUTPUT=stm32mp15_basic
|
||||||
# make stm32mp15_basic_defconfig
|
# make stm32mp15_basic_defconfig
|
||||||
# make DEVICE_TREE=stm32mp157c-ed1 all
|
# make DEVICE_TREE=stm32mp157c-ed1 all
|
||||||
|
|
||||||
e) basic boot on dk1::
|
e) basic boot on STM32MP15x dk1::
|
||||||
|
|
||||||
# export KBUILD_OUTPUT=stm32mp15_basic
|
# export KBUILD_OUTPUT=stm32mp15_basic
|
||||||
# make stm32mp15_basic_defconfig
|
# make stm32mp15_basic_defconfig
|
||||||
# make DEVICE_TREE=stm32mp157a-dk1 all
|
# make DEVICE_TREE=stm32mp157a-dk1 all
|
||||||
|
|
||||||
f) basic boot on avenger96::
|
f) basic boot on STM32MP15x avenger96::
|
||||||
|
|
||||||
# export KBUILD_OUTPUT=stm32mp15_basic
|
# export KBUILD_OUTPUT=stm32mp15_basic
|
||||||
# make stm32mp15_basic_defconfig
|
# make stm32mp15_basic_defconfig
|
||||||
@ -235,6 +292,7 @@ Build Procedure
|
|||||||
So in the output directory (selected by KBUILD_OUTPUT),
|
So in the output directory (selected by KBUILD_OUTPUT),
|
||||||
you can found the needed U-Boot files:
|
you can found the needed U-Boot files:
|
||||||
|
|
||||||
|
- stm32mp13_defconfig = **u-boot-nodtb.bin** and **u-boot.dtb**
|
||||||
- stm32mp15_defconfig = **u-boot-nodtb.bin** and **u-boot.dtb**
|
- stm32mp15_defconfig = **u-boot-nodtb.bin** and **u-boot.dtb**
|
||||||
|
|
||||||
- stm32mp15_trusted_defconfig = u-boot.stm32
|
- stm32mp15_trusted_defconfig = u-boot.stm32
|
||||||
@ -325,9 +383,9 @@ the boot pin values = BOOT0, BOOT1, BOOT2
|
|||||||
| SPI-NAND | 1 | 1 | 1 |
|
| SPI-NAND | 1 | 1 | 1 |
|
||||||
+-------------+---------+---------+---------+
|
+-------------+---------+---------+---------+
|
||||||
|
|
||||||
- on the **daugther board ed1 = MB1263** with the switch SW1
|
- on the STM32MP15x **daughter board ed1 = MB1263** with the switch SW1
|
||||||
- on **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable)
|
- on STM32MP15x **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable)
|
||||||
- on board **DK1/DK2** with the switch SW1 = BOOT0, BOOT2
|
- on board STM32MP15x **DK1/DK2** with the switch SW1 = BOOT0, BOOT2
|
||||||
with only 2 pins available (BOOT1 is forced to 0 and NOR not supported),
|
with only 2 pins available (BOOT1 is forced to 0 and NOR not supported),
|
||||||
the possible value becomes:
|
the possible value becomes:
|
||||||
|
|
||||||
@ -355,7 +413,7 @@ The communication between HOST and board is based on
|
|||||||
Prepare an SD card
|
Prepare an SD card
|
||||||
------------------
|
------------------
|
||||||
|
|
||||||
The minimal requirements for STMP32MP15x boot up to U-Boot are:
|
The minimal requirements for STMP32MP15x and STM32MP13x boot up to U-Boot are:
|
||||||
|
|
||||||
- GPT partitioning (with gdisk or with sgdisk)
|
- GPT partitioning (with gdisk or with sgdisk)
|
||||||
- 2 fsbl partitions, named "fsbl1" and "fsbl2", size at least 256KiB
|
- 2 fsbl partitions, named "fsbl1" and "fsbl2", size at least 256KiB
|
||||||
@ -511,14 +569,25 @@ MAC Address
|
|||||||
Please read doc/README.enetaddr for the implementation guidelines for mac id
|
Please read doc/README.enetaddr for the implementation guidelines for mac id
|
||||||
usage. Basically, environment has precedence over board specific storage.
|
usage. Basically, environment has precedence over board specific storage.
|
||||||
|
|
||||||
For STMicroelectonics board, it is retrieved in STM32MP15x OTP :
|
For STMicroelectronics board, it is retrieved in:
|
||||||
|
|
||||||
|
- STM32MP15x OTP:
|
||||||
|
|
||||||
- OTP_57[31:0] = MAC_ADDR[31:0]
|
- OTP_57[31:0] = MAC_ADDR[31:0]
|
||||||
- OTP_58[15:0] = MAC_ADDR[47:32]
|
- OTP_58[15:0] = MAC_ADDR[47:32]
|
||||||
|
|
||||||
To program a MAC address on virgin OTP words above, you can use the fuse command
|
- STM32MP13x OTP:
|
||||||
|
|
||||||
|
- OTP_57[31:0] = MAC_ADDR0[31:0]
|
||||||
|
- OTP_58[15:0] = MAC_ADDR0[47:32]
|
||||||
|
- OTP_58[31:16] = MAC_ADDR1[15:0]
|
||||||
|
- OTP_59[31:0] = MAC_ADDR1[47:16]
|
||||||
|
|
||||||
|
To program a MAC address on virgin STM32MP15x OTP words above, you can use the fuse command
|
||||||
on bank 0 to access to internal OTP and lock them:
|
on bank 0 to access to internal OTP and lock them:
|
||||||
|
|
||||||
|
In the next example we are using the 2 OTPs used on STM32MP15x.
|
||||||
|
|
||||||
Prerequisite: check if a MAC address isn't yet programmed in OTP
|
Prerequisite: check if a MAC address isn't yet programmed in OTP
|
||||||
|
|
||||||
1) check OTP: their value must be equal to 0::
|
1) check OTP: their value must be equal to 0::
|
||||||
@ -571,8 +640,8 @@ Example to set mac address "12:34:56:78:9a:bc"
|
|||||||
OTP are protected. It is already done for the board
|
OTP are protected. It is already done for the board
|
||||||
provided by STMicroelectronics.
|
provided by STMicroelectronics.
|
||||||
|
|
||||||
Coprocessor firmware
|
Coprocessor firmware on STM32MP15x
|
||||||
--------------------
|
----------------------------------
|
||||||
|
|
||||||
U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
|
U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
|
||||||
|
|
||||||
|
|||||||
@ -3,7 +3,8 @@ ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
|
|||||||
--------------------
|
--------------------
|
||||||
Required properties:
|
Required properties:
|
||||||
--------------------
|
--------------------
|
||||||
- compatible : Should be "st,stm32mp1-ddr"
|
- compatible : Should be "st,stm32mp1-ddr" for STM32MP15x
|
||||||
|
Should be "st,stm32mp13-ddr" for STM32MP13x
|
||||||
- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
|
- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
|
||||||
- clocks : controller clocks handle
|
- clocks : controller clocks handle
|
||||||
- clock-names : associated controller clock names
|
- clock-names : associated controller clock names
|
||||||
@ -13,6 +14,8 @@ Required properties:
|
|||||||
the next attributes are DDR parameters, they are generated by DDR tools
|
the next attributes are DDR parameters, they are generated by DDR tools
|
||||||
included in STM32 Cube tool
|
included in STM32 Cube tool
|
||||||
|
|
||||||
|
They are required only in SPL, when TFABOOT is not activated.
|
||||||
|
|
||||||
info attributes:
|
info attributes:
|
||||||
----------------
|
----------------
|
||||||
- st,mem-name : name for DDR configuration, simple string for information
|
- st,mem-name : name for DDR configuration, simple string for information
|
||||||
@ -24,7 +27,7 @@ controlleur attributes:
|
|||||||
-----------------------
|
-----------------------
|
||||||
- st,ctl-reg : controleur values depending of the DDR type
|
- st,ctl-reg : controleur values depending of the DDR type
|
||||||
(DDR3/LPDDR2/LPDDR3)
|
(DDR3/LPDDR2/LPDDR3)
|
||||||
for STM32MP15x: 25 values are requested in this order
|
for STM32MP15x and STM32MP13x: 25 values are requested in this order
|
||||||
MSTR
|
MSTR
|
||||||
MRCTRL0
|
MRCTRL0
|
||||||
MRCTRL1
|
MRCTRL1
|
||||||
@ -53,7 +56,7 @@ controlleur attributes:
|
|||||||
|
|
||||||
- st,ctl-timing : controleur values depending of frequency and timing parameter
|
- st,ctl-timing : controleur values depending of frequency and timing parameter
|
||||||
of DDR
|
of DDR
|
||||||
for STM32MP15x: 12 values are requested in this order
|
for STM32MP15x and STM32MP13x: 12 values are requested in this order
|
||||||
RFSHTMG
|
RFSHTMG
|
||||||
DRAMTMG0
|
DRAMTMG0
|
||||||
DRAMTMG1
|
DRAMTMG1
|
||||||
@ -68,7 +71,7 @@ controlleur attributes:
|
|||||||
ODTCFG
|
ODTCFG
|
||||||
|
|
||||||
- st,ctl-map : controleur values depending of address mapping
|
- st,ctl-map : controleur values depending of address mapping
|
||||||
for STM32MP15x: 9 values are requested in this order
|
for STM32MP15x and STM32MP13x: 9 values are requested in this order
|
||||||
ADDRMAP1
|
ADDRMAP1
|
||||||
ADDRMAP2
|
ADDRMAP2
|
||||||
ADDRMAP3
|
ADDRMAP3
|
||||||
@ -99,6 +102,19 @@ controlleur attributes:
|
|||||||
PCFGWQOS0_1
|
PCFGWQOS0_1
|
||||||
PCFGWQOS1_1
|
PCFGWQOS1_1
|
||||||
|
|
||||||
|
for STM32MP13x: 11 values are requested in this order
|
||||||
|
SCHED
|
||||||
|
SCHED1
|
||||||
|
PERFHPR1
|
||||||
|
PERFLPR1
|
||||||
|
PERFWR1
|
||||||
|
PCFGR_0
|
||||||
|
PCFGW_0
|
||||||
|
PCFGQOS0_0
|
||||||
|
PCFGQOS1_0
|
||||||
|
PCFGWQOS0_0
|
||||||
|
PCFGWQOS1_0
|
||||||
|
|
||||||
phyc attributes:
|
phyc attributes:
|
||||||
----------------
|
----------------
|
||||||
- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
|
- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
|
||||||
@ -115,8 +131,19 @@ phyc attributes:
|
|||||||
DX2GCR
|
DX2GCR
|
||||||
DX3GCR
|
DX3GCR
|
||||||
|
|
||||||
|
for STM32MP13x: 9 values are requested in this order
|
||||||
|
PGCR
|
||||||
|
ACIOCR
|
||||||
|
DXCCR
|
||||||
|
DSGCR
|
||||||
|
DCR
|
||||||
|
ODTCR
|
||||||
|
ZQ0CR1
|
||||||
|
DX0GCR
|
||||||
|
DX1GCR
|
||||||
|
|
||||||
- st,phy-timing : phy values depending of frequency and timing parameter of DDR
|
- st,phy-timing : phy values depending of frequency and timing parameter of DDR
|
||||||
for STM32MP15x: 10 values are requested in this order
|
for STM32MP15x and STM32MP13x: 10 values are requested in this order
|
||||||
PTR0
|
PTR0
|
||||||
PTR1
|
PTR1
|
||||||
PTR2
|
PTR2
|
||||||
@ -128,16 +155,18 @@ phyc attributes:
|
|||||||
MR2
|
MR2
|
||||||
MR3
|
MR3
|
||||||
|
|
||||||
|
for STM32MP13x: 6 values are requested in this order
|
||||||
|
DX0DLLCR
|
||||||
|
DX0DQTR
|
||||||
|
DX0DQSTR
|
||||||
|
DX1DLLCR
|
||||||
|
DX1DQTR
|
||||||
|
DX1DQSTR
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
soc {
|
soc {
|
||||||
u-boot,dm-spl;
|
|
||||||
|
|
||||||
ddr: ddr@0x5A003000{
|
ddr: ddr@0x5A003000{
|
||||||
u-boot,dm-spl;
|
|
||||||
u-boot,dm-pre-reloc;
|
|
||||||
|
|
||||||
compatible = "st,stm32mp1-ddr";
|
compatible = "st,stm32mp1-ddr";
|
||||||
|
|
||||||
reg = <0x5A003000 0x550
|
reg = <0x5A003000 0x550
|
||||||
|
|||||||
@ -166,22 +166,6 @@ config CLK_SCMI
|
|||||||
by a SCMI agent based on SCMI clock protocol communication
|
by a SCMI agent based on SCMI clock protocol communication
|
||||||
with a SCMI server.
|
with a SCMI server.
|
||||||
|
|
||||||
config CLK_STM32F
|
|
||||||
bool "Enable clock driver support for STM32F family"
|
|
||||||
depends on CLK && (STM32F7 || STM32F4)
|
|
||||||
default y
|
|
||||||
help
|
|
||||||
This clock driver adds support for RCC clock management
|
|
||||||
for STM32F4 and STM32F7 SoCs.
|
|
||||||
|
|
||||||
config CLK_STM32MP1
|
|
||||||
bool "Enable RCC clock driver for STM32MP1"
|
|
||||||
depends on ARCH_STM32MP && CLK
|
|
||||||
default y
|
|
||||||
help
|
|
||||||
Enable the STM32 clock (RCC) driver. Enable support for
|
|
||||||
manipulating STM32MP1's on-SoC clocks.
|
|
||||||
|
|
||||||
config CLK_HSDK
|
config CLK_HSDK
|
||||||
bool "Enable cgu clock driver for HSDK boards"
|
bool "Enable cgu clock driver for HSDK boards"
|
||||||
depends on CLK && TARGET_HSDK
|
depends on CLK && TARGET_HSDK
|
||||||
@ -251,6 +235,7 @@ source "drivers/clk/owl/Kconfig"
|
|||||||
source "drivers/clk/renesas/Kconfig"
|
source "drivers/clk/renesas/Kconfig"
|
||||||
source "drivers/clk/sunxi/Kconfig"
|
source "drivers/clk/sunxi/Kconfig"
|
||||||
source "drivers/clk/sifive/Kconfig"
|
source "drivers/clk/sifive/Kconfig"
|
||||||
|
source "drivers/clk/stm32/Kconfig"
|
||||||
source "drivers/clk/tegra/Kconfig"
|
source "drivers/clk/tegra/Kconfig"
|
||||||
source "drivers/clk/ti/Kconfig"
|
source "drivers/clk/ti/Kconfig"
|
||||||
source "drivers/clk/uniphier/Kconfig"
|
source "drivers/clk/uniphier/Kconfig"
|
||||||
|
|||||||
@ -23,6 +23,8 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
|
|||||||
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
|
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
|
||||||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
||||||
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
|
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
|
||||||
|
obj-$(CONFIG_ARCH_STM32) += stm32/
|
||||||
|
obj-$(CONFIG_ARCH_STM32MP) += stm32/
|
||||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||||
obj-$(CONFIG_CLK_AT91) += at91/
|
obj-$(CONFIG_CLK_AT91) += at91/
|
||||||
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
|
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
|
||||||
@ -39,8 +41,6 @@ obj-$(CONFIG_CLK_OWL) += owl/
|
|||||||
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
||||||
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
|
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
|
||||||
obj-$(CONFIG_CLK_SIFIVE) += sifive/
|
obj-$(CONFIG_CLK_SIFIVE) += sifive/
|
||||||
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
|
|
||||||
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
|
|
||||||
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
||||||
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
|
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
|
||||||
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
|
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
|
||||||
@ -53,4 +53,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
|
|||||||
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
|
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
|
||||||
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
|
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
|
||||||
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
|
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
|
||||||
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
|
|
||||||
|
|||||||
23
drivers/clk/stm32/Kconfig
Normal file
23
drivers/clk/stm32/Kconfig
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
config CLK_STM32F
|
||||||
|
bool "Enable clock driver support for STM32F family"
|
||||||
|
depends on CLK && (STM32F7 || STM32F4)
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This clock driver adds support for RCC clock management
|
||||||
|
for STM32F4 and STM32F7 SoCs.
|
||||||
|
|
||||||
|
config CLK_STM32H7
|
||||||
|
bool "Enable clock driver support for STM32H7 family"
|
||||||
|
depends on CLK && STM32H7
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This clock driver adds support for RCC clock management
|
||||||
|
for STM32H7 SoCs.
|
||||||
|
|
||||||
|
config CLK_STM32MP1
|
||||||
|
bool "Enable RCC clock driver for STM32MP15"
|
||||||
|
depends on ARCH_STM32MP && CLK
|
||||||
|
default y if STM32MP15x
|
||||||
|
help
|
||||||
|
Enable the STM32 clock (RCC) driver. Enable support for
|
||||||
|
manipulating STM32MP15's on-SoC clocks.
|
||||||
7
drivers/clk/stm32/Makefile
Normal file
7
drivers/clk/stm32/Makefile
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
#
|
||||||
|
# Copyright (C) 2022, STMicroelectronics - All Rights Reserved
|
||||||
|
|
||||||
|
obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o
|
||||||
|
obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o
|
||||||
|
obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o
|
||||||
@ -1,7 +1,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __DW_I2C_H_
|
#ifndef __DW_I2C_H_
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
* Copyright 2019 Google Inc
|
* Copyright 2019 Google Inc
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|||||||
@ -39,6 +39,11 @@ struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
|
|||||||
.soc = STM32MP1,
|
.soc = STM32MP1,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct stm32_rcc_clk stm32_rcc_clk_mp13 = {
|
||||||
|
.drv_name = "stm32mp13_clk",
|
||||||
|
.soc = STM32MP1,
|
||||||
|
};
|
||||||
|
|
||||||
static int stm32_rcc_bind(struct udevice *dev)
|
static int stm32_rcc_bind(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct udevice *child;
|
struct udevice *child;
|
||||||
@ -79,6 +84,7 @@ static const struct udevice_id stm32_rcc_ids[] = {
|
|||||||
{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
|
{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
|
||||||
{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
|
{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
|
||||||
{.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
|
{.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
|
||||||
|
{.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 },
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -514,10 +514,12 @@ retry_cmd:
|
|||||||
*/
|
*/
|
||||||
static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
|
static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
|
||||||
{
|
{
|
||||||
|
if (reset_valid(&priv->reset_ctl)) {
|
||||||
/* Reset */
|
/* Reset */
|
||||||
reset_assert(&priv->reset_ctl);
|
reset_assert(&priv->reset_ctl);
|
||||||
udelay(2);
|
udelay(2);
|
||||||
reset_deassert(&priv->reset_ctl);
|
reset_deassert(&priv->reset_ctl);
|
||||||
|
}
|
||||||
|
|
||||||
/* init the needed SDMMC register after reset */
|
/* init the needed SDMMC register after reset */
|
||||||
writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
|
writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
|
||||||
@ -735,7 +737,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
|
|||||||
|
|
||||||
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
|
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto clk_disable;
|
dev_dbg(dev, "No reset provided\n");
|
||||||
|
|
||||||
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
|
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
|
||||||
GPIOD_IS_IN);
|
GPIOD_IS_IN);
|
||||||
@ -755,8 +757,6 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
|
|||||||
stm32_sdmmc2_reset(priv);
|
stm32_sdmmc2_reset(priv);
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
clk_disable:
|
|
||||||
clk_disable(&priv->clk);
|
|
||||||
clk_free:
|
clk_free:
|
||||||
clk_free(&priv->clk);
|
clk_free(&priv->clk);
|
||||||
|
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2010
|
* (C) Copyright 2010
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2010
|
* (C) Copyright 2010
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef _DW_ETH_H
|
#ifndef _DW_ETH_H
|
||||||
|
|||||||
@ -272,7 +272,7 @@ config PINCTRL_STI
|
|||||||
depends on DM && ARCH_STI
|
depends on DM && ARCH_STI
|
||||||
default y
|
default y
|
||||||
help
|
help
|
||||||
Support pin multiplexing control on STMicrolectronics STi SoCs.
|
Support pin multiplexing control on STMicroelectronics STi SoCs.
|
||||||
|
|
||||||
The driver is controlled by a device tree node which contains both
|
The driver is controlled by a device tree node which contains both
|
||||||
the GPIO definitions and pin control functions for each available
|
the GPIO definitions and pin control functions for each available
|
||||||
|
|||||||
@ -488,6 +488,7 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
|
|||||||
{ .compatible = "st,stm32h743-pinctrl" },
|
{ .compatible = "st,stm32h743-pinctrl" },
|
||||||
{ .compatible = "st,stm32mp157-pinctrl" },
|
{ .compatible = "st,stm32mp157-pinctrl" },
|
||||||
{ .compatible = "st,stm32mp157-z-pinctrl" },
|
{ .compatible = "st,stm32mp157-z-pinctrl" },
|
||||||
|
{ .compatible = "st,stm32mp135-pinctrl" },
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -230,29 +230,29 @@ static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)
|
|||||||
|
|
||||||
reg = readl(&ctl->addrmap3);
|
reg = readl(&ctl->addrmap3);
|
||||||
/* addrmap3.addrmap_col_b6 */
|
/* addrmap3.addrmap_col_b6 */
|
||||||
val = (reg & GENMASK(3, 0)) >> 0;
|
val = (reg & GENMASK(4, 0)) >> 0;
|
||||||
if (val <= 7)
|
if (val <= 7)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap3.addrmap_col_b7 */
|
/* addrmap3.addrmap_col_b7 */
|
||||||
val = (reg & GENMASK(11, 8)) >> 8;
|
val = (reg & GENMASK(12, 8)) >> 8;
|
||||||
if (val <= 7)
|
if (val <= 7)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap3.addrmap_col_b8 */
|
/* addrmap3.addrmap_col_b8 */
|
||||||
val = (reg & GENMASK(19, 16)) >> 16;
|
val = (reg & GENMASK(20, 16)) >> 16;
|
||||||
if (val <= 7)
|
if (val <= 7)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap3.addrmap_col_b9 */
|
/* addrmap3.addrmap_col_b9 */
|
||||||
val = (reg & GENMASK(27, 24)) >> 24;
|
val = (reg & GENMASK(28, 24)) >> 24;
|
||||||
if (val <= 7)
|
if (val <= 7)
|
||||||
bits++;
|
bits++;
|
||||||
|
|
||||||
reg = readl(&ctl->addrmap4);
|
reg = readl(&ctl->addrmap4);
|
||||||
/* addrmap4.addrmap_col_b10 */
|
/* addrmap4.addrmap_col_b10 */
|
||||||
val = (reg & GENMASK(3, 0)) >> 0;
|
val = (reg & GENMASK(4, 0)) >> 0;
|
||||||
if (val <= 7)
|
if (val <= 7)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap4.addrmap_col_b11 */
|
/* addrmap4.addrmap_col_b11 */
|
||||||
val = (reg & GENMASK(11, 8)) >> 8;
|
val = (reg & GENMASK(12, 8)) >> 8;
|
||||||
if (val <= 7)
|
if (val <= 7)
|
||||||
bits++;
|
bits++;
|
||||||
|
|
||||||
@ -296,21 +296,24 @@ static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
|
|||||||
reg = readl(&ctl->addrmap6);
|
reg = readl(&ctl->addrmap6);
|
||||||
/* addrmap6.addrmap_row_b12 */
|
/* addrmap6.addrmap_row_b12 */
|
||||||
val = (reg & GENMASK(3, 0)) >> 0;
|
val = (reg & GENMASK(3, 0)) >> 0;
|
||||||
if (val <= 7)
|
if (val <= 11)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap6.addrmap_row_b13 */
|
/* addrmap6.addrmap_row_b13 */
|
||||||
val = (reg & GENMASK(11, 8)) >> 8;
|
val = (reg & GENMASK(11, 8)) >> 8;
|
||||||
if (val <= 7)
|
if (val <= 11)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap6.addrmap_row_b14 */
|
/* addrmap6.addrmap_row_b14 */
|
||||||
val = (reg & GENMASK(19, 16)) >> 16;
|
val = (reg & GENMASK(19, 16)) >> 16;
|
||||||
if (val <= 7)
|
if (val <= 11)
|
||||||
bits++;
|
bits++;
|
||||||
/* addrmap6.addrmap_row_b15 */
|
/* addrmap6.addrmap_row_b15 */
|
||||||
val = (reg & GENMASK(27, 24)) >> 24;
|
val = (reg & GENMASK(27, 24)) >> 24;
|
||||||
if (val <= 7)
|
if (val <= 11)
|
||||||
bits++;
|
bits++;
|
||||||
|
|
||||||
|
if (reg & BIT(31))
|
||||||
|
printf("warning: LPDDR3_6GB_12GB is not supported\n");
|
||||||
|
|
||||||
return bits;
|
return bits;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -392,12 +395,17 @@ static struct ram_ops stm32mp1_ddr_ops = {
|
|||||||
.get_info = stm32mp1_ddr_get_info,
|
.get_info = stm32mp1_ddr_get_info,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct stm32mp1_ddr_cfg stm32mp13x_ddr_cfg = {
|
||||||
|
.nb_bytes = 2,
|
||||||
|
};
|
||||||
|
|
||||||
static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
|
static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
|
||||||
.nb_bytes = 4,
|
.nb_bytes = 4,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct udevice_id stm32mp1_ddr_ids[] = {
|
static const struct udevice_id stm32mp1_ddr_ids[] = {
|
||||||
{ .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
|
{ .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
|
||||||
|
{ .compatible = "st,stm32mp13-ddr", .data = (ulong)&stm32mp13x_ddr_cfg},
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
* TI OMAP1510 USB bus interface driver
|
* TI OMAP1510 USB bus interface driver
|
||||||
*
|
*
|
||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
|||||||
100
include/configs/stm32mp13_common.h
Normal file
100
include/configs/stm32mp13_common.h
Normal file
@ -0,0 +1,100 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
|
||||||
|
*
|
||||||
|
* Configuration settings for the STM32MP13x CPU
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_STM32MP13_COMMMON_H
|
||||||
|
#define __CONFIG_STM32MP13_COMMMON_H
|
||||||
|
#include <linux/sizes.h>
|
||||||
|
#include <asm/arch/stm32.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration of the external SRAM memory used by U-Boot
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, use the first 256 MB of memory, since this is
|
||||||
|
* the maximum mapped by the Linux kernel during initialization.
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_BOOTMAPSZ SZ_256M
|
||||||
|
|
||||||
|
/* Extend size of kernel image for uncompression */
|
||||||
|
#define CONFIG_SYS_BOOTM_LEN SZ_32M
|
||||||
|
|
||||||
|
/*MMC SD*/
|
||||||
|
#define CONFIG_SYS_MMC_MAX_DEVICE 2
|
||||||
|
|
||||||
|
/* NAND support */
|
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||||
|
|
||||||
|
/*****************************************************************************/
|
||||||
|
#ifdef CONFIG_DISTRO_DEFAULTS
|
||||||
|
/*****************************************************************************/
|
||||||
|
|
||||||
|
#ifdef CONFIG_CMD_MMC
|
||||||
|
#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
|
||||||
|
#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
|
||||||
|
#else
|
||||||
|
#define BOOT_TARGET_MMC0(func)
|
||||||
|
#define BOOT_TARGET_MMC1(func)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define BOOT_TARGET_DEVICES(func) \
|
||||||
|
BOOT_TARGET_MMC1(func) \
|
||||||
|
BOOT_TARGET_MMC0(func)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* default bootcmd for stm32mp13:
|
||||||
|
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
|
||||||
|
*/
|
||||||
|
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
|
||||||
|
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
|
||||||
|
"run env_check;" \
|
||||||
|
"if test ${boot_device} = mmc;" \
|
||||||
|
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
|
||||||
|
"run distro_bootcmd;" \
|
||||||
|
"fi;\0"
|
||||||
|
|
||||||
|
#define STM32MP_EXTRA \
|
||||||
|
"env_check=if env info -p -d -q; then env save; fi\0" \
|
||||||
|
"boot_net_usb_start=true\0"
|
||||||
|
|
||||||
|
#ifndef STM32MP_BOARD_EXTRA_ENV
|
||||||
|
#define STM32MP_BOARD_EXTRA_ENV
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <config_distro_bootcmd.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* memory layout for 32M uncompressed/compressed kernel,
|
||||||
|
* 1M fdt, 1M script, 1M pxe and 1M for overlay
|
||||||
|
* and the ramdisk at the end.
|
||||||
|
*/
|
||||||
|
#define __KERNEL_ADDR_R __stringify(0xc2000000)
|
||||||
|
#define __FDT_ADDR_R __stringify(0xc4000000)
|
||||||
|
#define __SCRIPT_ADDR_R __stringify(0xc4100000)
|
||||||
|
#define __PXEFILE_ADDR_R __stringify(0xc4200000)
|
||||||
|
#define __FDTOVERLAY_ADDR_R __stringify(0xc4300000)
|
||||||
|
#define __RAMDISK_ADDR_R __stringify(0xc4400000)
|
||||||
|
|
||||||
|
#define STM32MP_MEM_LAYOUT \
|
||||||
|
"kernel_addr_r=" __KERNEL_ADDR_R "\0" \
|
||||||
|
"fdt_addr_r=" __FDT_ADDR_R "\0" \
|
||||||
|
"scriptaddr=" __SCRIPT_ADDR_R "\0" \
|
||||||
|
"pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
|
||||||
|
"fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
|
||||||
|
"ramdisk_addr_r=" __RAMDISK_ADDR_R "\0"
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
STM32MP_MEM_LAYOUT \
|
||||||
|
STM32MP_BOOTCMD \
|
||||||
|
BOOTENV \
|
||||||
|
STM32MP_EXTRA \
|
||||||
|
STM32MP_BOARD_EXTRA_ENV
|
||||||
|
|
||||||
|
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
|
||||||
|
|
||||||
|
#endif /* __CONFIG_STM32MP13_COMMMON_H */
|
||||||
17
include/configs/stm32mp13_st_common.h
Normal file
17
include/configs/stm32mp13_st_common.h
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
|
||||||
|
*
|
||||||
|
* Configuration settings for the STMicroelectronics STM32MP13x boards
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_STM32MP13_ST_COMMON_H__
|
||||||
|
#define __CONFIG_STM32MP13_ST_COMMON_H__
|
||||||
|
|
||||||
|
#define STM32MP_BOARD_EXTRA_ENV \
|
||||||
|
"usb_pgood_delay=1000\0" \
|
||||||
|
"console=ttySTM0\0"
|
||||||
|
|
||||||
|
#include <configs/stm32mp13_common.h>
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -15,10 +15,6 @@
|
|||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
|
#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
|
||||||
|
|
||||||
/*
|
|
||||||
* Console I/O buffer size
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For booting Linux, use the first 256 MB of memory, since this is
|
* For booting Linux, use the first 256 MB of memory, since this is
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
* the maximum mapped by the Linux kernel during initialization.
|
||||||
@ -28,13 +24,6 @@
|
|||||||
/* Extend size of kernel image for uncompression */
|
/* Extend size of kernel image for uncompression */
|
||||||
#define CONFIG_SYS_BOOTM_LEN SZ_32M
|
#define CONFIG_SYS_BOOTM_LEN SZ_32M
|
||||||
|
|
||||||
/* SPL support */
|
|
||||||
#ifdef CONFIG_SPL
|
|
||||||
/* SPL use DDR */
|
|
||||||
|
|
||||||
/* Restrict SPL to fit within SYSRAM */
|
|
||||||
#define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE)
|
|
||||||
#endif /* #ifdef CONFIG_SPL */
|
|
||||||
/*MMC SD*/
|
/*MMC SD*/
|
||||||
#define CONFIG_SYS_MMC_MAX_DEVICE 3
|
#define CONFIG_SYS_MMC_MAX_DEVICE 3
|
||||||
|
|
||||||
@ -90,7 +79,7 @@
|
|||||||
BOOT_TARGET_PXE(func)
|
BOOT_TARGET_PXE(func)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* default bootcmd for stm32mp1:
|
* default bootcmd for stm32mp15:
|
||||||
* for serial/usb: execute the stm32prog command
|
* for serial/usb: execute the stm32prog command
|
||||||
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
|
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
|
||||||
* for nand or spi-nand boot, distro boot with ubifs on UBI partition
|
* for nand or spi-nand boot, distro boot with ubifs on UBI partition
|
||||||
|
|||||||
@ -2,7 +2,7 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
|
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
|
||||||
*
|
*
|
||||||
* Configuration settings for the STMicroelectonics STM32MP15x boards
|
* Configuration settings for the STMicroelectronics STM32MP15x boards
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CONFIG_STM32MP15_ST_COMMON_H__
|
#ifndef __CONFIG_STM32MP15_ST_COMMON_H__
|
||||||
|
|||||||
@ -188,14 +188,14 @@ typedef struct {
|
|||||||
#define EM_NDR1 57 /* Denso NDR1 microprocessor */
|
#define EM_NDR1 57 /* Denso NDR1 microprocessor */
|
||||||
#define EM_STARCORE 58 /* Motorola Start*Core processor */
|
#define EM_STARCORE 58 /* Motorola Start*Core processor */
|
||||||
#define EM_ME16 59 /* Toyota ME16 processor */
|
#define EM_ME16 59 /* Toyota ME16 processor */
|
||||||
#define EM_ST100 60 /* STMicroelectronic ST100 processor */
|
#define EM_ST100 60 /* STMicroelectronics ST100 processor */
|
||||||
#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/
|
#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/
|
||||||
#define EM_X86_64 62 /* AMD x86-64 */
|
#define EM_X86_64 62 /* AMD x86-64 */
|
||||||
#define EM_PDSP 63 /* Sony DSP Processor */
|
#define EM_PDSP 63 /* Sony DSP Processor */
|
||||||
/* RESERVED 64,65 for future use */
|
/* RESERVED 64,65 for future use */
|
||||||
#define EM_FX66 66 /* Siemens FX66 microcontroller */
|
#define EM_FX66 66 /* Siemens FX66 microcontroller */
|
||||||
#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */
|
#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */
|
||||||
#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */
|
#define EM_ST7 68 /* STMicroelectronics ST7 8 bit mc */
|
||||||
#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */
|
#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */
|
||||||
#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */
|
#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */
|
||||||
#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */
|
#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2010
|
* (C) Copyright 2010
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __FSMC_NAND_H__
|
#ifndef __FSMC_NAND_H__
|
||||||
|
|||||||
@ -23,12 +23,9 @@
|
|||||||
|
|
||||||
/* BUCKS_MRST_CR */
|
/* BUCKS_MRST_CR */
|
||||||
#define STPMIC1_MRST_BUCK(buck) BIT(buck)
|
#define STPMIC1_MRST_BUCK(buck) BIT(buck)
|
||||||
#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
|
|
||||||
STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
|
|
||||||
|
|
||||||
/* LDOS_MRST_CR */
|
/* LDOS_MRST_CR */
|
||||||
#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
|
#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
|
||||||
#define STPMIC1_MRST_LDO_DEBUG 0
|
|
||||||
|
|
||||||
/* BUCKx_MAIN_CR (x=1...4) */
|
/* BUCKx_MAIN_CR (x=1...4) */
|
||||||
#define STPMIC1_BUCK_ENA BIT(0)
|
#define STPMIC1_BUCK_ENA BIT(0)
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2009
|
* (C) Copyright 2009
|
||||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __DW_UDC_H
|
#ifndef __DW_UDC_H
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user