mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-13 20:36:02 +01:00
mmc: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland
parent
6af2813d18
commit
308f433167
@ -1,139 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2007-2011
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
* Aaron <leafy.myeh@allwinnertech.com>
|
||||
*
|
||||
* MMC register definition for allwinner sunxi platform.
|
||||
*/
|
||||
|
||||
#ifndef _SUNXI_MMC_H
|
||||
#define _SUNXI_MMC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct sunxi_mmc {
|
||||
u32 gctrl; /* 0x00 global control */
|
||||
u32 clkcr; /* 0x04 clock control */
|
||||
u32 timeout; /* 0x08 time out */
|
||||
u32 width; /* 0x0c bus width */
|
||||
u32 blksz; /* 0x10 block size */
|
||||
u32 bytecnt; /* 0x14 byte count */
|
||||
u32 cmd; /* 0x18 command */
|
||||
u32 arg; /* 0x1c argument */
|
||||
u32 resp0; /* 0x20 response 0 */
|
||||
u32 resp1; /* 0x24 response 1 */
|
||||
u32 resp2; /* 0x28 response 2 */
|
||||
u32 resp3; /* 0x2c response 3 */
|
||||
u32 imask; /* 0x30 interrupt mask */
|
||||
u32 mint; /* 0x34 masked interrupt status */
|
||||
u32 rint; /* 0x38 raw interrupt status */
|
||||
u32 status; /* 0x3c status */
|
||||
u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
|
||||
u32 funcsel; /* 0x44 function select */
|
||||
u32 cbcr; /* 0x48 CIU byte count */
|
||||
u32 bbcr; /* 0x4c BIU byte count */
|
||||
u32 dbgc; /* 0x50 debug enable */
|
||||
u32 res0; /* 0x54 reserved */
|
||||
u32 a12a; /* 0x58 Auto command 12 argument */
|
||||
u32 ntsr; /* 0x5c New timing set register */
|
||||
u32 res1[8];
|
||||
u32 dmac; /* 0x80 internal DMA control */
|
||||
u32 dlba; /* 0x84 internal DMA descr list base address */
|
||||
u32 idst; /* 0x88 internal DMA status */
|
||||
u32 idie; /* 0x8c internal DMA interrupt enable */
|
||||
u32 chda; /* 0x90 */
|
||||
u32 cbda; /* 0x94 */
|
||||
u32 res2[26];
|
||||
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
|
||||
u32 res3[17];
|
||||
u32 samp_dl;
|
||||
u32 res4[46];
|
||||
#endif
|
||||
u32 fifo; /* 0x100 / 0x200 FIFO access address */
|
||||
};
|
||||
|
||||
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
|
||||
#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
|
||||
#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
|
||||
|
||||
#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
|
||||
#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
|
||||
#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
|
||||
#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
|
||||
SUNXI_MMC_GCTRL_FIFO_RESET|\
|
||||
SUNXI_MMC_GCTRL_DMA_RESET)
|
||||
#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
|
||||
#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
|
||||
|
||||
#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
|
||||
#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
|
||||
#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
|
||||
#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
|
||||
#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
|
||||
#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
|
||||
#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
|
||||
#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
|
||||
#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
|
||||
#define SUNXI_MMC_CMD_START (0x1 << 31)
|
||||
|
||||
#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
|
||||
#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
|
||||
#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
|
||||
#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
|
||||
#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
|
||||
#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
|
||||
#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
|
||||
#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
|
||||
#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
|
||||
#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
|
||||
#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
|
||||
#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
|
||||
#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
|
||||
#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
|
||||
#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
|
||||
#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
|
||||
#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
|
||||
#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
|
||||
#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
|
||||
(SUNXI_MMC_RINT_RESP_ERROR | \
|
||||
SUNXI_MMC_RINT_RESP_CRC_ERROR | \
|
||||
SUNXI_MMC_RINT_DATA_CRC_ERROR | \
|
||||
SUNXI_MMC_RINT_RESP_TIMEOUT | \
|
||||
SUNXI_MMC_RINT_DATA_TIMEOUT | \
|
||||
SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
|
||||
SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
|
||||
SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
|
||||
SUNXI_MMC_RINT_START_BIT_ERROR | \
|
||||
SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
|
||||
#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
|
||||
(SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
|
||||
SUNXI_MMC_RINT_DATA_OVER | \
|
||||
SUNXI_MMC_RINT_COMMAND_DONE | \
|
||||
SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
|
||||
|
||||
#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
|
||||
#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
|
||||
#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
|
||||
#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
|
||||
#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
|
||||
#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
|
||||
#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
|
||||
#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
|
||||
|
||||
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
|
||||
|
||||
#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
|
||||
#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
|
||||
#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
|
||||
|
||||
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
|
||||
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
|
||||
|
||||
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
|
||||
#define SUNXI_MMC_COMMON_RESET (1 << 18)
|
||||
|
||||
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
|
||||
#ifndef _ARCH_SUNXI_MMC_H
|
||||
#define _ARCH_SUNXI_MMC_H
|
||||
|
||||
struct mmc *sunxi_mmc_init(int sdc_no);
|
||||
#endif /* _SUNXI_MMC_H */
|
||||
|
||||
#endif /* _ARCH_SUNXI_MMC_H */
|
||||
|
||||
@ -114,6 +114,7 @@ static inline u16 readw(const volatile void __iomem *addr)
|
||||
return val;
|
||||
}
|
||||
|
||||
#define readl_relaxed readl
|
||||
static inline u32 readl(const volatile void __iomem *addr)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
@ -727,7 +727,8 @@ config ZYNQ_HISPD_BROKEN
|
||||
|
||||
config MMC_SUNXI
|
||||
bool "Allwinner sunxi SD/MMC Host Controller support"
|
||||
depends on ARCH_SUNXI && !UART0_PORT_F
|
||||
depends on (ARCH_SUNXI || TARGET_SUNXI) && !UART0_PORT_F
|
||||
depends on DM_GPIO || !DM_MMC
|
||||
default y
|
||||
help
|
||||
This selects support for the SD/MMC Host Controller on
|
||||
|
||||
@ -17,15 +17,34 @@
|
||||
#include <reset.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#if !CONFIG_IS_ENABLED(DM_MMC)
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/mmc.h>
|
||||
#endif
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "sunxi_mmc.h"
|
||||
|
||||
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
|
||||
#define CCM_MMC_CTRL_MODE_SEL_NEW 0
|
||||
#endif
|
||||
|
||||
#include "../../arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h"
|
||||
|
||||
unsigned int clock_get_pll6(void)
|
||||
{
|
||||
struct sunxi_ccm_reg *const ccm =
|
||||
(struct sunxi_ccm_reg *)0x2001000UL;
|
||||
|
||||
uint32_t rval = readl(&ccm->pll6_cfg);
|
||||
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
|
||||
int m = ((rval >> 1) & 0x1) + 1;
|
||||
int p0 = ((rval >> 16) & 0x7) + 1;
|
||||
/* The register defines PLL6-2X, not plain PLL6 */
|
||||
return 24000000 / n / m / p0;
|
||||
}
|
||||
|
||||
struct sunxi_mmc_plat {
|
||||
struct mmc_config cfg;
|
||||
struct mmc mmc;
|
||||
@ -113,7 +132,8 @@ static bool sunxi_mmc_can_calibrate(void)
|
||||
return IS_ENABLED(CONFIG_MACH_SUN50I) ||
|
||||
IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
|
||||
IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
|
||||
IS_ENABLED(CONFIG_MACH_SUN8I_R40);
|
||||
IS_ENABLED(CONFIG_MACH_SUN8I_R40) ||
|
||||
IS_ENABLED(CONFIG_MACH_SUN20I);
|
||||
}
|
||||
|
||||
static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
|
||||
@ -247,7 +267,7 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
|
||||
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
|
||||
writel(rval, &priv->reg->clkcr);
|
||||
|
||||
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
|
||||
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_MACH_SUN20I)
|
||||
/* A64 supports calibration of delays on MMC controller and we
|
||||
* have to set delay of zero before starting calibration.
|
||||
* Allwinner BSP driver sets a delay only in the case of
|
||||
@ -686,6 +706,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
|
||||
return ret;
|
||||
ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
|
||||
|
||||
#define SUNXI_MMC0_BASE 0x4020000
|
||||
priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
|
||||
priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
|
||||
|
||||
@ -727,6 +748,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
|
||||
{ .compatible = "allwinner,sun7i-a20-mmc" },
|
||||
{ .compatible = "allwinner,sun8i-a83t-emmc" },
|
||||
{ .compatible = "allwinner,sun9i-a80-mmc" },
|
||||
{ .compatible = "allwinner,sun20i-d1-mmc" },
|
||||
{ .compatible = "allwinner,sun50i-a64-mmc" },
|
||||
{ .compatible = "allwinner,sun50i-a64-emmc" },
|
||||
{ .compatible = "allwinner,sun50i-h6-mmc" },
|
||||
|
||||
136
drivers/mmc/sunxi_mmc.h
Normal file
136
drivers/mmc/sunxi_mmc.h
Normal file
@ -0,0 +1,136 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2007-2011
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
* Aaron <leafy.myeh@allwinnertech.com>
|
||||
*
|
||||
* MMC register definition for allwinner sunxi platform.
|
||||
*/
|
||||
|
||||
#ifndef _SUNXI_MMC_H
|
||||
#define _SUNXI_MMC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct sunxi_mmc {
|
||||
u32 gctrl; /* 0x00 global control */
|
||||
u32 clkcr; /* 0x04 clock control */
|
||||
u32 timeout; /* 0x08 time out */
|
||||
u32 width; /* 0x0c bus width */
|
||||
u32 blksz; /* 0x10 block size */
|
||||
u32 bytecnt; /* 0x14 byte count */
|
||||
u32 cmd; /* 0x18 command */
|
||||
u32 arg; /* 0x1c argument */
|
||||
u32 resp0; /* 0x20 response 0 */
|
||||
u32 resp1; /* 0x24 response 1 */
|
||||
u32 resp2; /* 0x28 response 2 */
|
||||
u32 resp3; /* 0x2c response 3 */
|
||||
u32 imask; /* 0x30 interrupt mask */
|
||||
u32 mint; /* 0x34 masked interrupt status */
|
||||
u32 rint; /* 0x38 raw interrupt status */
|
||||
u32 status; /* 0x3c status */
|
||||
u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
|
||||
u32 funcsel; /* 0x44 function select */
|
||||
u32 cbcr; /* 0x48 CIU byte count */
|
||||
u32 bbcr; /* 0x4c BIU byte count */
|
||||
u32 dbgc; /* 0x50 debug enable */
|
||||
u32 res0; /* 0x54 reserved */
|
||||
u32 a12a; /* 0x58 Auto command 12 argument */
|
||||
u32 ntsr; /* 0x5c New timing set register */
|
||||
u32 res1[8];
|
||||
u32 dmac; /* 0x80 internal DMA control */
|
||||
u32 dlba; /* 0x84 internal DMA descr list base address */
|
||||
u32 idst; /* 0x88 internal DMA status */
|
||||
u32 idie; /* 0x8c internal DMA interrupt enable */
|
||||
u32 chda; /* 0x90 */
|
||||
u32 cbda; /* 0x94 */
|
||||
u32 res2[26];
|
||||
u32 res3[17];
|
||||
u32 samp_dl;
|
||||
u32 res4[46];
|
||||
u32 fifo; /* 0x100 / 0x200 FIFO access address */
|
||||
};
|
||||
|
||||
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
|
||||
#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
|
||||
#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
|
||||
|
||||
#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
|
||||
#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
|
||||
#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
|
||||
#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
|
||||
SUNXI_MMC_GCTRL_FIFO_RESET|\
|
||||
SUNXI_MMC_GCTRL_DMA_RESET)
|
||||
#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
|
||||
#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
|
||||
|
||||
#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
|
||||
#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
|
||||
#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
|
||||
#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
|
||||
#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
|
||||
#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
|
||||
#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
|
||||
#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
|
||||
#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
|
||||
#define SUNXI_MMC_CMD_START (0x1 << 31)
|
||||
|
||||
#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
|
||||
#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
|
||||
#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
|
||||
#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
|
||||
#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
|
||||
#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
|
||||
#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
|
||||
#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
|
||||
#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
|
||||
#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
|
||||
#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
|
||||
#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
|
||||
#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
|
||||
#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
|
||||
#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
|
||||
#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
|
||||
#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
|
||||
#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
|
||||
#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
|
||||
(SUNXI_MMC_RINT_RESP_ERROR | \
|
||||
SUNXI_MMC_RINT_RESP_CRC_ERROR | \
|
||||
SUNXI_MMC_RINT_DATA_CRC_ERROR | \
|
||||
SUNXI_MMC_RINT_RESP_TIMEOUT | \
|
||||
SUNXI_MMC_RINT_DATA_TIMEOUT | \
|
||||
SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
|
||||
SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
|
||||
SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
|
||||
SUNXI_MMC_RINT_START_BIT_ERROR | \
|
||||
SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
|
||||
#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
|
||||
(SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
|
||||
SUNXI_MMC_RINT_DATA_OVER | \
|
||||
SUNXI_MMC_RINT_COMMAND_DONE | \
|
||||
SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
|
||||
|
||||
#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
|
||||
#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
|
||||
#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
|
||||
#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
|
||||
#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
|
||||
#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
|
||||
#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
|
||||
#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
|
||||
|
||||
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
|
||||
|
||||
#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
|
||||
#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
|
||||
#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
|
||||
|
||||
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
|
||||
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
|
||||
|
||||
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
|
||||
#define SUNXI_MMC_COMMON_RESET (1 << 18)
|
||||
|
||||
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
|
||||
|
||||
#endif /* _SUNXI_MMC_H */
|
||||
Loading…
x
Reference in New Issue
Block a user