random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-14 04:46:01 +01:00
Code Issues Packages Projects Releases Wiki Activity

rockchip: rk3288-cru: sync the clock dt-binding header from Linux

Browse Source 
In order to update the DT for rk3288
sync the clock dt-binding header.
This is the state as of v5.17 in Linux.
Keep SCLK_MAC_PLL in use for rk3288 clock driver.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Johan Jonker 2022-04-15 23:21:38 +02:00 committed by Kever Yang
parent 444311196e
commit 334d519a13
1 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
include/dt-bindings/clock/rk3288-cru.h
View File

@ -1,9 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
* Copyright (c) 2014 MundoReader S.L. * Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de> * Author: Heiko Stuebner <heiko@sntech.de>
*/ */
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
/* core clocks */ /* core clocks */
#define PLL_APLL 1 #define PLL_APLL 1
#define PLL_DPLL 2 #define PLL_DPLL 2
@ -74,6 +77,9 @@
#define SCLK_USBPHY480M_SRC 122 #define SCLK_USBPHY480M_SRC 122
#define SCLK_PVTM_CORE 123 #define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124 #define SCLK_PVTM_GPU 124
#define SCLK_CRYPTO 125
#define SCLK_MIPIDSI_24M 126
#define SCLK_VIP_OUT 127
#define SCLK_MAC_PLL 150 #define SCLK_MAC_PLL 150
#define SCLK_MAC 151 #define SCLK_MAC 151
@ -153,6 +159,9 @@
#define PCLK_DDRUPCTL1 366 #define PCLK_DDRUPCTL1 366
#define PCLK_PUBL1 367 #define PCLK_PUBL1 367
#define PCLK_WDT 368 #define PCLK_WDT 368
#define PCLK_EFUSE256 369
#define PCLK_EFUSE1024 370
#define PCLK_ISP_IN 371
/* hclk gates */ /* hclk gates */
#define HCLK_GPS 448 #define HCLK_GPS 448
@ -368,3 +377,5 @@
#define SRST_TSP_CLKIN0 189 #define SRST_TSP_CLKIN0 189
#define SRST_TSP_CLKIN1 190 #define SRST_TSP_CLKIN1 190
#define SRST_TSP_27M 191 #define SRST_TSP_27M 191
#endif