mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
This commit is contained in:
Tom Rini
commit
446a30d2a0
@ -975,9 +975,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
|
||||
imxrt1020-evk.dtb \
|
||||
imxrt1170-evk.dtb \
|
||||
|
||||
dtb-$(CONFIG_TARGET_RZG2L) += \
|
||||
r9a07g044l2-smarc.dts
|
||||
|
||||
ifdef CONFIG_RCAR_64
|
||||
DTC_FLAGS += -R 4 -p 0x1000
|
||||
endif
|
||||
|
||||
8
arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi
Normal file
8
arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi
Normal file
@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2M board
|
||||
*
|
||||
* Copyright (C) 2021-2024 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include "r8a774a1-u-boot.dtsi"
|
||||
@ -1,26 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2M board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include "r8a774a1-u-boot.dtsi"
|
||||
|
||||
&gpio3 {
|
||||
bt_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "bt-reg-on";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
wlan_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "wlan-reg-on";
|
||||
};
|
||||
};
|
||||
@ -10,45 +10,3 @@
|
||||
&extalr_clk {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &audma1;
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &csi20;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &fcpf0;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvd2;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &hdmi0;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &sound_card;
|
||||
/delete-node/ &vin0;
|
||||
/delete-node/ &vin1;
|
||||
/delete-node/ &vin2;
|
||||
/delete-node/ &vin3;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &vin6;
|
||||
/delete-node/ &vin7;
|
||||
/delete-node/ &vspb;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspd2;
|
||||
/delete-node/ &vspi0;
|
||||
|
||||
/ {
|
||||
/delete-node/ hdmi0-out;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ fdp1@fe940000;
|
||||
};
|
||||
};
|
||||
|
||||
8
arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi
Normal file
8
arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi
Normal file
@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
|
||||
*
|
||||
* Copyright (C) 2021-2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774b1-u-boot.dtsi"
|
||||
@ -1,26 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774b1-u-boot.dtsi"
|
||||
|
||||
&gpio3 {
|
||||
bt_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "bt-reg-on";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
wlan_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "wlan-reg-on";
|
||||
};
|
||||
};
|
||||
@ -10,43 +10,3 @@
|
||||
&extalr_clk {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &audma1;
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &csi20;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &fcpf0;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &hdmi0;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &sound_card;
|
||||
/delete-node/ &vin0;
|
||||
/delete-node/ &vin1;
|
||||
/delete-node/ &vin2;
|
||||
/delete-node/ &vin3;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &vin6;
|
||||
/delete-node/ &vin7;
|
||||
/delete-node/ &vspb;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspi0;
|
||||
|
||||
/ {
|
||||
/delete-node/ hdmi0-out;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ fdp1@fe940000;
|
||||
};
|
||||
};
|
||||
|
||||
8
arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi
Normal file
8
arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi
Normal file
@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
|
||||
*
|
||||
* Copyright (C) 2020-2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774e1-u-boot.dtsi"
|
||||
@ -1,26 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774e1-u-boot.dtsi"
|
||||
|
||||
&gpio3 {
|
||||
bt_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "bt-reg-on";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
wlan_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "wlan-reg-on";
|
||||
};
|
||||
};
|
||||
@ -10,49 +10,3 @@
|
||||
&extalr_clk {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &audma1;
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &csi20;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &fcpf0;
|
||||
/delete-node/ &fcpf1;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvb1;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &fcpvi1;
|
||||
/delete-node/ &hdmi0;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &sound_card;
|
||||
/delete-node/ &vin0;
|
||||
/delete-node/ &vin1;
|
||||
/delete-node/ &vin2;
|
||||
/delete-node/ &vin3;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &vin6;
|
||||
/delete-node/ &vin7;
|
||||
/delete-node/ &vspbc;
|
||||
/delete-node/ &vspbd;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspi0;
|
||||
/delete-node/ &vspi1;
|
||||
|
||||
/ {
|
||||
/delete-node/ hdmi0-out;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ fdp1@fe940000;
|
||||
/delete-node/ fdp1@fe944000;
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,39 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/G2L SMARC EVK board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
|
||||
#define PMOD1_SER0 1
|
||||
|
||||
/*
|
||||
* To enable MTU3a PWM on PMOD0,
|
||||
* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
|
||||
* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
|
||||
*/
|
||||
#define PMOD_MTU3 0
|
||||
|
||||
#if (PMOD_MTU3 && PMOD1_SER0)
|
||||
#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
|
||||
#endif
|
||||
|
||||
#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
|
||||
|
||||
#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
|
||||
#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
|
||||
#endif
|
||||
|
||||
#include "r9a07g044l2.dtsi"
|
||||
#include "rzg2l-smarc-som.dtsi"
|
||||
#include "rzg2l-smarc-pinfunction.dtsi"
|
||||
#include "rz-smarc-common.dtsi"
|
||||
#include "rzg2l-smarc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas SMARC EVK based on r9a07g044l2";
|
||||
compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
|
||||
};
|
||||
@ -1,13 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r9a07g044.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
|
||||
};
|
||||
@ -1,183 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
|
||||
*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/*
|
||||
* SSI-WM8978
|
||||
*
|
||||
* This command is required when Playback/Capture
|
||||
*
|
||||
* amixer cset name='Left Input Mixer L2 Switch' on
|
||||
* amixer cset name='Right Input Mixer R2 Switch' on
|
||||
* amixer cset name='Headphone Playback Volume' 100
|
||||
* amixer cset name='PCM Volume' 100%
|
||||
* amixer cset name='Input PGA Volume' 25
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
snd_rzg2l: sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,bitclock-master = <&cpu_dai>;
|
||||
simple-audio-card,frame-master = <&cpu_dai>;
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,widgets = "Microphone", "Microphone Jack";
|
||||
simple-audio-card,routing =
|
||||
"L2", "Mic Bias",
|
||||
"R2", "Mic Bias",
|
||||
"Mic Bias", "Microphone Jack";
|
||||
|
||||
cpu_dai: simple-audio-card,cpu {
|
||||
};
|
||||
|
||||
codec_dai: simple-audio-card,codec {
|
||||
clocks = <&versa3 2>;
|
||||
sound-dai = <&wm8978>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_vbus_otg: regulator-usb0-vbus-otg {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "USB0_VBUS_OTG";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
x1: x1-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk1 {
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
&audio_clk2 {
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&can0_pins &can1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vbus-supply = <&usb0_vbus_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
@ -1,157 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-0 = <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
can0_pins: can0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
|
||||
<RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
|
||||
};
|
||||
|
||||
/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
|
||||
can0-stb-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "can0_stb";
|
||||
};
|
||||
|
||||
can1_pins: can1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
|
||||
<RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
|
||||
};
|
||||
|
||||
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
|
||||
can1-stb-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "can1_stb";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
pins = "RIIC0_SDA", "RIIC0_SCL";
|
||||
input-enable;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
pins = "RIIC1_SDA", "RIIC1_SCL";
|
||||
input-enable;
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
|
||||
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
|
||||
};
|
||||
|
||||
mtu3_pins: mtu3 {
|
||||
mtu3-ext-clk-input-pin {
|
||||
pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
|
||||
<RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
|
||||
};
|
||||
|
||||
mtu3-pwm {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
|
||||
<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
|
||||
<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
|
||||
<RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
|
||||
};
|
||||
|
||||
#if MTU3_COUNTER_Z_PHASE_SIGNAL
|
||||
mtu3-zphase-clk {
|
||||
pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
|
||||
};
|
||||
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
|
||||
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
|
||||
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
|
||||
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
|
||||
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
|
||||
};
|
||||
|
||||
sd1-pwr-en-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "sd1_pwr_en";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
sd1_data {
|
||||
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sd1_ctrl {
|
||||
pins = "SD1_CLK", "SD1_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sd1_mux {
|
||||
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
|
||||
};
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
sd1_data_uhs {
|
||||
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd1_ctrl_uhs {
|
||||
pins = "SD1_CLK", "SD1_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd1_mux_uhs {
|
||||
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
|
||||
};
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
pins = "AUDIO_CLK1", "AUDIO_CLK2";
|
||||
input-enable;
|
||||
};
|
||||
|
||||
spi1_pins: spi1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
|
||||
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
|
||||
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
|
||||
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
|
||||
};
|
||||
|
||||
ssi0_pins: ssi0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
|
||||
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
|
||||
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
|
||||
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
|
||||
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
|
||||
<RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
|
||||
<RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,371 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
|
||||
#define EMMC 1
|
||||
|
||||
/*
|
||||
* To enable uSD card on CN3,
|
||||
* SW1[2] should be at position 3/ON.
|
||||
* Disable eMMC by setting "#define EMMC 0" above.
|
||||
*/
|
||||
#define SDHI (!EMMC)
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_1p1v: regulator-vdd-core {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.1V";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
regulator-boot-on;
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x2: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
pinctrl-0 = <&adc_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/delete-node/ channel@6;
|
||||
/delete-node/ channel@7;
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <7>;
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
|
||||
rxc-skew-psec = <2400>;
|
||||
txc-skew-psec = <2400>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txen-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ð1 {
|
||||
pinctrl-0 = <ð1_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-id0022.1640",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <7>;
|
||||
interrupt-parent = <&irqc>;
|
||||
interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
|
||||
rxc-skew-psec = <2400>;
|
||||
txc-skew-psec = <2400>;
|
||||
rxdv-skew-psec = <0>;
|
||||
txen-skew-psec = <0>;
|
||||
rxd0-skew-psec = <0>;
|
||||
rxd1-skew-psec = <0>;
|
||||
rxd2-skew-psec = <0>;
|
||||
rxd3-skew-psec = <0>;
|
||||
txd0-skew-psec = <0>;
|
||||
txd1-skew-psec = <0>;
|
||||
txd2-skew-psec = <0>;
|
||||
txd3-skew-psec = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <®_1p1v>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
raa215300: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
|
||||
clocks = <&x2>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
adc_pins: adc {
|
||||
pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
|
||||
};
|
||||
|
||||
eth0_pins: eth0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
|
||||
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
|
||||
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
|
||||
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
|
||||
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
|
||||
<RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
|
||||
};
|
||||
|
||||
eth1_pins: eth1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
|
||||
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
|
||||
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
|
||||
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
|
||||
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
|
||||
<RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
|
||||
};
|
||||
|
||||
gpio-sd0-pwr-en-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "gpio_sd0_pwr_en";
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
qspi0-data {
|
||||
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi0-ctrl {
|
||||
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
|
||||
* The below switch logic can be used to select the device between
|
||||
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
|
||||
* SW1[2] should be at position 2/OFF to enable 64 GB eMMC
|
||||
* SW1[2] should be at position 3/ON to enable uSD card CN3
|
||||
*/
|
||||
sd0-dev-sel-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "sd0_dev_sel";
|
||||
};
|
||||
|
||||
sdhi0_emmc_pins: sd0emmc {
|
||||
sd0_emmc_data {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_emmc_ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_emmc_rst {
|
||||
pins = "SD0_RST#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
sd0_data {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sd0_ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sd0_mux {
|
||||
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
sd0_data_uhs {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_ctrl_uhs {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0_mux_uhs {
|
||||
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sbc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "micron,mt25qu512a", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot@0 {
|
||||
reg = <0x00000000 0x2000000>;
|
||||
read-only;
|
||||
};
|
||||
user@2000000 {
|
||||
reg = <0x2000000 0x2000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if SDHI
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
#if EMMC
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_emmc_pins>;
|
||||
pinctrl-1 = <&sdhi0_emmc_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
fixed-emmc-driver-type = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
status = "okay";
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
@ -1,181 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial1 = &scif2;
|
||||
i2c3 = &i2c3;
|
||||
};
|
||||
|
||||
osc1: cec-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "d";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7535_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_dai {
|
||||
sound-dai = <&ssi0>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&adv7535_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
adv7535: hdmi@3d {
|
||||
compatible = "adi,adv7535";
|
||||
reg = <0x3d>;
|
||||
|
||||
interrupt-parent = <&pinctrl>;
|
||||
interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&osc1>;
|
||||
clock-names = "cec";
|
||||
avdd-supply = <®_1p8v>;
|
||||
dvdd-supply = <®_1p8v>;
|
||||
pvdd-supply = <®_1p8v>;
|
||||
a2vdd-supply = <®_1p8v>;
|
||||
v3p3-supply = <®_3p3v>;
|
||||
v1p2-supply = <®_1p8v>;
|
||||
|
||||
adi,dsi-lanes = <4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7535_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7535_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
wm8978: codec@1a {
|
||||
compatible = "wlf,wm8978";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
versa3: clock-generator@68 {
|
||||
compatible = "renesas,5p35023";
|
||||
reg = <0x68>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&x1>;
|
||||
|
||||
renesas,settings = [
|
||||
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
|
||||
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
|
||||
80 b0 45 c4 95
|
||||
];
|
||||
|
||||
assigned-clocks = <&versa3 0>, <&versa3 1>,
|
||||
<&versa3 2>, <&versa3 3>,
|
||||
<&versa3 4>, <&versa3 5>;
|
||||
assigned-clock-rates = <24000000>, <11289600>,
|
||||
<11289600>, <12000000>,
|
||||
<25000000>, <12288000>;
|
||||
};
|
||||
};
|
||||
|
||||
#if PMOD_MTU3
|
||||
&mtu3 {
|
||||
pinctrl-0 = <&mtu3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#if MTU3_COUNTER_Z_PHASE_SIGNAL
|
||||
/* SDHI cd pin is muxed with counter Z phase signal */
|
||||
&sdhi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
|
||||
|
||||
&spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
#endif /* PMOD_MTU3 */
|
||||
|
||||
/*
|
||||
* To enable SCIF2 (SER0) on PMOD1 (CN7)
|
||||
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
|
||||
* SW2 should be at position 2->3 so that SER0_TX line is activated
|
||||
* SW3 should be at position 2->3 so that SER0_RX line is activated
|
||||
* SW4 should be at position 2->3 so that SER0_RTS# line is activated
|
||||
*/
|
||||
#if PMOD1_SER0
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&ssi0 {
|
||||
pinctrl-0 = <&ssi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vccq_sdhi1 {
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
@ -8,6 +8,6 @@
|
||||
#define __ASM_ARCH_RZG2L_H
|
||||
|
||||
#define GICD_BASE 0x11900000
|
||||
#define GICR_BASE 0x11960000
|
||||
#define GICR_BASE 0x11940000
|
||||
|
||||
#endif /* __ASM_ARCH_RZG2L_H */
|
||||
|
||||
@ -96,15 +96,15 @@ static bool is_hoperun_hihope_rzg2_board(const char *board_name)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
|
||||
!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
|
||||
!strcmp(name, "r8a774a1-hihope-rzg2m-ex"))
|
||||
return 0;
|
||||
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
|
||||
!strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
|
||||
!strcmp(name, "r8a774b1-hihope-rzg2n-ex"))
|
||||
return 0;
|
||||
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
|
||||
!strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
|
||||
!strcmp(name, "r8a774e1-hihope-rzg2h-ex"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
RENESAS RZG2L BOARD FAMILY
|
||||
M: Paul Barker <paul.barker.ct@bp.renesas.com>
|
||||
S: Supported
|
||||
F: arch/arm/dts/rz-smarc-common.dtsi
|
||||
N: rz-smarc
|
||||
N: rzg2l
|
||||
N: r9a07g044
|
||||
|
||||
@ -8,23 +8,23 @@ CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_TEXT_BASE=0x50000000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0xFFFE0000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m-ex"
|
||||
CONFIG_TARGET_HIHOPE_RZG2=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000"
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
|
||||
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m-ex.dtb; booti 0x48080000 - 0x48000000"
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m-ex.dtb"
|
||||
# CONFIG_BOARD_EARLY_INIT_F is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m renesas/r8a774b1-hihope-rzg2n renesas/r8a774e1-hihope-rzg2h"
|
||||
CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m-ex renesas/r8a774b1-hihope-rzg2n-ex renesas/r8a774e1-hihope-rzg2h-ex"
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_MMC_ENV_DEV=0
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
|
||||
@ -1,220 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R9A07G044 CPG Core Clocks */
|
||||
#define R9A07G044_CLK_I 0
|
||||
#define R9A07G044_CLK_I2 1
|
||||
#define R9A07G044_CLK_G 2
|
||||
#define R9A07G044_CLK_S0 3
|
||||
#define R9A07G044_CLK_S1 4
|
||||
#define R9A07G044_CLK_SPI0 5
|
||||
#define R9A07G044_CLK_SPI1 6
|
||||
#define R9A07G044_CLK_SD0 7
|
||||
#define R9A07G044_CLK_SD1 8
|
||||
#define R9A07G044_CLK_M0 9
|
||||
#define R9A07G044_CLK_M1 10
|
||||
#define R9A07G044_CLK_M2 11
|
||||
#define R9A07G044_CLK_M3 12
|
||||
#define R9A07G044_CLK_M4 13
|
||||
#define R9A07G044_CLK_HP 14
|
||||
#define R9A07G044_CLK_TSU 15
|
||||
#define R9A07G044_CLK_ZT 16
|
||||
#define R9A07G044_CLK_P0 17
|
||||
#define R9A07G044_CLK_P1 18
|
||||
#define R9A07G044_CLK_P2 19
|
||||
#define R9A07G044_CLK_AT 20
|
||||
#define R9A07G044_OSCCLK 21
|
||||
#define R9A07G044_CLK_P0_DIV2 22
|
||||
|
||||
/* R9A07G044 Module Clocks */
|
||||
#define R9A07G044_CA55_SCLK 0
|
||||
#define R9A07G044_CA55_PCLK 1
|
||||
#define R9A07G044_CA55_ATCLK 2
|
||||
#define R9A07G044_CA55_GICCLK 3
|
||||
#define R9A07G044_CA55_PERICLK 4
|
||||
#define R9A07G044_CA55_ACLK 5
|
||||
#define R9A07G044_CA55_TSCLK 6
|
||||
#define R9A07G044_GIC600_GICCLK 7
|
||||
#define R9A07G044_IA55_CLK 8
|
||||
#define R9A07G044_IA55_PCLK 9
|
||||
#define R9A07G044_MHU_PCLK 10
|
||||
#define R9A07G044_SYC_CNT_CLK 11
|
||||
#define R9A07G044_DMAC_ACLK 12
|
||||
#define R9A07G044_DMAC_PCLK 13
|
||||
#define R9A07G044_OSTM0_PCLK 14
|
||||
#define R9A07G044_OSTM1_PCLK 15
|
||||
#define R9A07G044_OSTM2_PCLK 16
|
||||
#define R9A07G044_MTU_X_MCK_MTU3 17
|
||||
#define R9A07G044_POE3_CLKM_POE 18
|
||||
#define R9A07G044_GPT_PCLK 19
|
||||
#define R9A07G044_POEG_A_CLKP 20
|
||||
#define R9A07G044_POEG_B_CLKP 21
|
||||
#define R9A07G044_POEG_C_CLKP 22
|
||||
#define R9A07G044_POEG_D_CLKP 23
|
||||
#define R9A07G044_WDT0_PCLK 24
|
||||
#define R9A07G044_WDT0_CLK 25
|
||||
#define R9A07G044_WDT1_PCLK 26
|
||||
#define R9A07G044_WDT1_CLK 27
|
||||
#define R9A07G044_WDT2_PCLK 28
|
||||
#define R9A07G044_WDT2_CLK 29
|
||||
#define R9A07G044_SPI_CLK2 30
|
||||
#define R9A07G044_SPI_CLK 31
|
||||
#define R9A07G044_SDHI0_IMCLK 32
|
||||
#define R9A07G044_SDHI0_IMCLK2 33
|
||||
#define R9A07G044_SDHI0_CLK_HS 34
|
||||
#define R9A07G044_SDHI0_ACLK 35
|
||||
#define R9A07G044_SDHI1_IMCLK 36
|
||||
#define R9A07G044_SDHI1_IMCLK2 37
|
||||
#define R9A07G044_SDHI1_CLK_HS 38
|
||||
#define R9A07G044_SDHI1_ACLK 39
|
||||
#define R9A07G044_GPU_CLK 40
|
||||
#define R9A07G044_GPU_AXI_CLK 41
|
||||
#define R9A07G044_GPU_ACE_CLK 42
|
||||
#define R9A07G044_ISU_ACLK 43
|
||||
#define R9A07G044_ISU_PCLK 44
|
||||
#define R9A07G044_H264_CLK_A 45
|
||||
#define R9A07G044_H264_CLK_P 46
|
||||
#define R9A07G044_CRU_SYSCLK 47
|
||||
#define R9A07G044_CRU_VCLK 48
|
||||
#define R9A07G044_CRU_PCLK 49
|
||||
#define R9A07G044_CRU_ACLK 50
|
||||
#define R9A07G044_MIPI_DSI_PLLCLK 51
|
||||
#define R9A07G044_MIPI_DSI_SYSCLK 52
|
||||
#define R9A07G044_MIPI_DSI_ACLK 53
|
||||
#define R9A07G044_MIPI_DSI_PCLK 54
|
||||
#define R9A07G044_MIPI_DSI_VCLK 55
|
||||
#define R9A07G044_MIPI_DSI_LPCLK 56
|
||||
#define R9A07G044_LCDC_CLK_A 57
|
||||
#define R9A07G044_LCDC_CLK_P 58
|
||||
#define R9A07G044_LCDC_CLK_D 59
|
||||
#define R9A07G044_SSI0_PCLK2 60
|
||||
#define R9A07G044_SSI0_PCLK_SFR 61
|
||||
#define R9A07G044_SSI1_PCLK2 62
|
||||
#define R9A07G044_SSI1_PCLK_SFR 63
|
||||
#define R9A07G044_SSI2_PCLK2 64
|
||||
#define R9A07G044_SSI2_PCLK_SFR 65
|
||||
#define R9A07G044_SSI3_PCLK2 66
|
||||
#define R9A07G044_SSI3_PCLK_SFR 67
|
||||
#define R9A07G044_SRC_CLKP 68
|
||||
#define R9A07G044_USB_U2H0_HCLK 69
|
||||
#define R9A07G044_USB_U2H1_HCLK 70
|
||||
#define R9A07G044_USB_U2P_EXR_CPUCLK 71
|
||||
#define R9A07G044_USB_PCLK 72
|
||||
#define R9A07G044_ETH0_CLK_AXI 73
|
||||
#define R9A07G044_ETH0_CLK_CHI 74
|
||||
#define R9A07G044_ETH1_CLK_AXI 75
|
||||
#define R9A07G044_ETH1_CLK_CHI 76
|
||||
#define R9A07G044_I2C0_PCLK 77
|
||||
#define R9A07G044_I2C1_PCLK 78
|
||||
#define R9A07G044_I2C2_PCLK 79
|
||||
#define R9A07G044_I2C3_PCLK 80
|
||||
#define R9A07G044_SCIF0_CLK_PCK 81
|
||||
#define R9A07G044_SCIF1_CLK_PCK 82
|
||||
#define R9A07G044_SCIF2_CLK_PCK 83
|
||||
#define R9A07G044_SCIF3_CLK_PCK 84
|
||||
#define R9A07G044_SCIF4_CLK_PCK 85
|
||||
#define R9A07G044_SCI0_CLKP 86
|
||||
#define R9A07G044_SCI1_CLKP 87
|
||||
#define R9A07G044_IRDA_CLKP 88
|
||||
#define R9A07G044_RSPI0_CLKB 89
|
||||
#define R9A07G044_RSPI1_CLKB 90
|
||||
#define R9A07G044_RSPI2_CLKB 91
|
||||
#define R9A07G044_CANFD_PCLK 92
|
||||
#define R9A07G044_GPIO_HCLK 93
|
||||
#define R9A07G044_ADC_ADCLK 94
|
||||
#define R9A07G044_ADC_PCLK 95
|
||||
#define R9A07G044_TSU_PCLK 96
|
||||
|
||||
/* R9A07G044 Resets */
|
||||
#define R9A07G044_CA55_RST_1_0 0
|
||||
#define R9A07G044_CA55_RST_1_1 1
|
||||
#define R9A07G044_CA55_RST_3_0 2
|
||||
#define R9A07G044_CA55_RST_3_1 3
|
||||
#define R9A07G044_CA55_RST_4 4
|
||||
#define R9A07G044_CA55_RST_5 5
|
||||
#define R9A07G044_CA55_RST_6 6
|
||||
#define R9A07G044_CA55_RST_7 7
|
||||
#define R9A07G044_CA55_RST_8 8
|
||||
#define R9A07G044_CA55_RST_9 9
|
||||
#define R9A07G044_CA55_RST_10 10
|
||||
#define R9A07G044_CA55_RST_11 11
|
||||
#define R9A07G044_CA55_RST_12 12
|
||||
#define R9A07G044_GIC600_GICRESET_N 13
|
||||
#define R9A07G044_GIC600_DBG_GICRESET_N 14
|
||||
#define R9A07G044_IA55_RESETN 15
|
||||
#define R9A07G044_MHU_RESETN 16
|
||||
#define R9A07G044_DMAC_ARESETN 17
|
||||
#define R9A07G044_DMAC_RST_ASYNC 18
|
||||
#define R9A07G044_SYC_RESETN 19
|
||||
#define R9A07G044_OSTM0_PRESETZ 20
|
||||
#define R9A07G044_OSTM1_PRESETZ 21
|
||||
#define R9A07G044_OSTM2_PRESETZ 22
|
||||
#define R9A07G044_MTU_X_PRESET_MTU3 23
|
||||
#define R9A07G044_POE3_RST_M_REG 24
|
||||
#define R9A07G044_GPT_RST_C 25
|
||||
#define R9A07G044_POEG_A_RST 26
|
||||
#define R9A07G044_POEG_B_RST 27
|
||||
#define R9A07G044_POEG_C_RST 28
|
||||
#define R9A07G044_POEG_D_RST 29
|
||||
#define R9A07G044_WDT0_PRESETN 30
|
||||
#define R9A07G044_WDT1_PRESETN 31
|
||||
#define R9A07G044_WDT2_PRESETN 32
|
||||
#define R9A07G044_SPI_RST 33
|
||||
#define R9A07G044_SDHI0_IXRST 34
|
||||
#define R9A07G044_SDHI1_IXRST 35
|
||||
#define R9A07G044_GPU_RESETN 36
|
||||
#define R9A07G044_GPU_AXI_RESETN 37
|
||||
#define R9A07G044_GPU_ACE_RESETN 38
|
||||
#define R9A07G044_ISU_ARESETN 39
|
||||
#define R9A07G044_ISU_PRESETN 40
|
||||
#define R9A07G044_H264_X_RESET_VCP 41
|
||||
#define R9A07G044_H264_CP_PRESET_P 42
|
||||
#define R9A07G044_CRU_CMN_RSTB 43
|
||||
#define R9A07G044_CRU_PRESETN 44
|
||||
#define R9A07G044_CRU_ARESETN 45
|
||||
#define R9A07G044_MIPI_DSI_CMN_RSTB 46
|
||||
#define R9A07G044_MIPI_DSI_ARESET_N 47
|
||||
#define R9A07G044_MIPI_DSI_PRESET_N 48
|
||||
#define R9A07G044_LCDC_RESET_N 49
|
||||
#define R9A07G044_SSI0_RST_M2_REG 50
|
||||
#define R9A07G044_SSI1_RST_M2_REG 51
|
||||
#define R9A07G044_SSI2_RST_M2_REG 52
|
||||
#define R9A07G044_SSI3_RST_M2_REG 53
|
||||
#define R9A07G044_SRC_RST 54
|
||||
#define R9A07G044_USB_U2H0_HRESETN 55
|
||||
#define R9A07G044_USB_U2H1_HRESETN 56
|
||||
#define R9A07G044_USB_U2P_EXL_SYSRST 57
|
||||
#define R9A07G044_USB_PRESETN 58
|
||||
#define R9A07G044_ETH0_RST_HW_N 59
|
||||
#define R9A07G044_ETH1_RST_HW_N 60
|
||||
#define R9A07G044_I2C0_MRST 61
|
||||
#define R9A07G044_I2C1_MRST 62
|
||||
#define R9A07G044_I2C2_MRST 63
|
||||
#define R9A07G044_I2C3_MRST 64
|
||||
#define R9A07G044_SCIF0_RST_SYSTEM_N 65
|
||||
#define R9A07G044_SCIF1_RST_SYSTEM_N 66
|
||||
#define R9A07G044_SCIF2_RST_SYSTEM_N 67
|
||||
#define R9A07G044_SCIF3_RST_SYSTEM_N 68
|
||||
#define R9A07G044_SCIF4_RST_SYSTEM_N 69
|
||||
#define R9A07G044_SCI0_RST 70
|
||||
#define R9A07G044_SCI1_RST 71
|
||||
#define R9A07G044_IRDA_RST 72
|
||||
#define R9A07G044_RSPI0_RST 73
|
||||
#define R9A07G044_RSPI1_RST 74
|
||||
#define R9A07G044_RSPI2_RST 75
|
||||
#define R9A07G044_CANFD_RSTP_N 76
|
||||
#define R9A07G044_CANFD_RSTC_N 77
|
||||
#define R9A07G044_GPIO_RSTN 78
|
||||
#define R9A07G044_GPIO_PORT_RESETN 79
|
||||
#define R9A07G044_GPIO_SPARE_RESETN 80
|
||||
#define R9A07G044_ADC_PRESETN 81
|
||||
#define R9A07G044_ADC_ADRST_N 82
|
||||
#define R9A07G044_TSU_PRESETN 83
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
|
||||
@ -1,25 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* This header provides constants for Renesas RZ/G2L family IRQC bindings.
|
||||
*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IRQC_RZG2L_H
|
||||
#define __DT_BINDINGS_IRQC_RZG2L_H
|
||||
|
||||
/* NMI maps to SPI0 */
|
||||
#define RZG2L_NMI 0
|
||||
|
||||
/* IRQ0-7 map to SPI1-8 */
|
||||
#define RZG2L_IRQ0 1
|
||||
#define RZG2L_IRQ1 2
|
||||
#define RZG2L_IRQ2 3
|
||||
#define RZG2L_IRQ3 4
|
||||
#define RZG2L_IRQ4 5
|
||||
#define RZG2L_IRQ5 6
|
||||
#define RZG2L_IRQ6 7
|
||||
#define RZG2L_IRQ7 8
|
||||
|
||||
#endif /* __DT_BINDINGS_IRQC_RZG2L_H */
|
||||
@ -1,23 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* This header provides constants for Renesas RZ/G2L family pinctrl bindings.
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
|
||||
#define __DT_BINDINGS_RZG2L_PINCTRL_H
|
||||
|
||||
#define RZG2L_PINS_PER_PORT 8
|
||||
|
||||
/*
|
||||
* Create the pin index from its bank and position numbers and store in
|
||||
* the upper 16 bits the alternate function identifier
|
||||
*/
|
||||
#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
|
||||
|
||||
/* Convert a port and pin label to its global pin index */
|
||||
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
|
||||
|
||||
#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */
|
||||
Loading…
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Reference in New Issue
Block a user