mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
SDRAM seems to be working on delta board, though u-boot doesn't start yet.
This commit is contained in:
Markus Klotzbcher
Markus Klotzbcher
parent
4f7a0e3671
commit
48b6242aa1
@ -49,6 +49,20 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
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bls 0b
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.endm
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#define SDRAM_CMD_NOP 0x40000000
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.macro do_nop_cmd num
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ldr r2, =MDMRS
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ldr r3, =SDRAM_CMD_NOP
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ldr r4, =0x0
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loop:
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str r3, [r2]
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add r4, r4, #1
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cmp r4, \num
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bls loop
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.endm
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/*
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* Memory setup
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*/
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@ -58,38 +72,14 @@ lowlevel_init:
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/* Set up GPIO pins first ----------------------------------------- */
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mov r10, lr
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/* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
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ldr r0, =0x40E10438 @ GPIO41 FFRXD
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ldr r1, =0x802
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str r1, [r0]
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/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
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ldr r0, =GPIO97
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ldr r1, =0x801
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str r1, [r0]
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ldr r0, =0x40E1043C @ GPIO42 FFTXD
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10440 @ GPIO43 FFCTS
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10444 @ GPIO 44 FFDCD
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10448 @ GPIO 45 FFDSR
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E1044C @ GPIO 46 FFRI
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10450 @ GPIO 47 FFDTR
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =0x40E10454 @ GPIO 48
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ldr r1, =0x802
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str r1, [r0]
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ldr r0, =GPIO98
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ldr r1, =0x801
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str r1, [r0]
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/* tebrandt - ASCR, clear the RDH bit */
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ldr r0, =ASCR
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@ -99,10 +89,6 @@ lowlevel_init:
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/* ---------------------------------------------------------------- */
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/* Enable memory interface */
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/* */
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/* The sequence below is based on the recommended init steps */
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/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
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/* Chapter 10. */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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@ -110,21 +96,67 @@ lowlevel_init:
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* ---------------------------------------------------------------- */
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/* mk: replaced with wait macro */
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/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
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/* mov r2, #0 */
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/* str r2, [r3] */
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/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
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/* /\* so 0x300 should be plenty *\/ */
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/* 1: */
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/* ldr r2, [r3] */
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/* cmp r4, r2 */
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/* bgt 1b */
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wait #300
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mem_init:
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#define NEW_SDRAM_INIT 1
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#ifdef NEW_SDRAM_INIT
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/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
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ldr r0, =ACCR
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ldr r1, [r0]
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orr r1, r1, #0x3000
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str r1, [r0]
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ldr r1, [r0]
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/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
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ldr r0, =MDCNFG
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ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
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/* ldr r1, =0x80000403 */
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str r1, [r0]
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ldr r1, [r0] /* delay until written */
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/* 3. wait nop power up waiting period (200ms)
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* optimization: Steps 4+6 can be done during this
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*/
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wait #300
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/* 4. Perform an initial Rcomp-calibration cycle */
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ldr r0, =RCOMP
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ldr r1, =0x80000000
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str r1, [r0]
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ldr r1, [r0] /* delay until written */
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/* missing: program for automatic rcomp evaluation cycles */
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/* 5. DDR DRAM strobe delay calibration */
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ldr r0, =DDR_HCAL
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ldr r1, =0x88000007
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str r1, [r0]
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wait #5
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ldr r1, [r0] /* delay until written */
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/* Set MDMRS */
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ldr r0, =MDMRS
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ldr r1, =0x60000023
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str r1, [r0]
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wait #300
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/* Configure MDREFR */
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ldr r0, =MDREFR
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ldr r1, =0x00000006
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str r1, [r0]
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ldr r1, [r0]
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/* Enable the dynamic memory controller */
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ldr r0, =MDCNFG
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ldr r1, [r0]
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orr r1, r1, #MDCNFG_DMCEN
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str r1, [r0]
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#else /* NEW_SDRAM_INIT */
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/* configure the MEMCLKCFG register */
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ldr r1, =MEMCLKCFG
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ldr r2, =0x00010001
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@ -235,6 +267,8 @@ mem_init:
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orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
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str r1, [r0]
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#endif /* NEW_SDRAM_INIT */
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/* scrub/init SDRAM if enabled/present */
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/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
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/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
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@ -270,18 +304,9 @@ mem_init:
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mov r0,#0x80000000
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mcr p14,0,r0,c10,c0,0 // dcsr
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/* We are finished with Intel's memory controller initialisation */
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/* ---------------------------------------------------------------- */
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/* End lowlevel_init */
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/* ---------------------------------------------------------------- */
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endlowlevel_init:
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mov pc, lr
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mov pc, lr
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/*
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@ -1994,6 +1994,31 @@ typedef void (*ExcpHndlr) (void) ;
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#define PAD_SCLK __REG_2(0x4810012C)
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#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
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/* Some frequently used bits */
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#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
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#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
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#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
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#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
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#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
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#define MDCNFG_DTC_1 0x100
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#define MDCNFG_DTC_2 0x200
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#define MDCNFG_DTC_3 0x300
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#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
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#define MDCNFG_DRAC_13 0x20
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#define MDCNFG_DRAC_14 0x40
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#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
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#define MDCNFG_DCAC_10 0x08
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#define MDCNFG_DCAC_11 0x10
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#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
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#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
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#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
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/* Data Flash Controller Registers */
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