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powerpc/85xx: Add basic support for P1010RDB
Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal
Kumar Gala
parent
14aa71e660
commit
49249e137d
52
board/freescale/p1010rdb/Makefile
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52
board/freescale/p1010rdb/Makefile
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@ -0,0 +1,52 @@
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#
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# Copyright 2010-2011 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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250
board/freescale/p1010rdb/ddr.c
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250
board/freescale/p1010rdb/ddr.c
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@ -0,0 +1,250 @@
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_DDR_RAW_TIMING
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#define CONFIG_SYS_DRAM_SIZE 1024
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fixed_ddr_parm_t fixed_ddr_parm_0[] = {
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{750, 850, &ddr_cfg_regs_800},
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{607, 749, &ddr_cfg_regs_667},
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{0, 0, NULL}
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};
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unsigned long get_sdram_size(void)
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{
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struct cpu_type *cpu;
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phys_size_t ddr_size;
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cpu = gd->cpu;
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/* P1014 and it's derivatives support max 16it DDR width */
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if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
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ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
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else
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ddr_size = CONFIG_SYS_DRAM_SIZE;
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return ddr_size;
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}
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram(void)
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{
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int i;
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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phys_size_t ddr_size;
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ulong ddr_freq, ddr_freq_mhz;
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struct cpu_type *cpu;
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#if defined(CONFIG_SYS_RAMBOOT)
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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#endif
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ddr_freq = get_ddr_freq(0);
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ddr_freq_mhz = ddr_freq / 1000000;
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
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if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
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(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
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memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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break;
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}
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}
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if (fixed_ddr_parm_0[i].max_freq == 0)
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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cpu = gd->cpu;
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/* P1014 and it's derivatives support max 16bit DDR width */
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if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
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ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
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ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
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ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
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ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000;
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}
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ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
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LAW_TRGT_IF_DDR_1) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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return ddr_size;
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}
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#else /* CONFIG_DDR_RAW_TIMING */
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/*
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* Samsung K4B2G0846C-HCF8
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* The following timing are for "downshift"
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* i.e. to use CL9 part as CL7
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* otherwise, tAA, tRCD, tRP will be 13500ps
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* and tRC will be 49500ps
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*/
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1875,
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.caslat_X = 0x1e << 4, /* 5,6,7,8 */
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.tAA_ps = 13125,
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.tWR_ps = 15000,
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.tRCD_ps = 13125,
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.tRRD_ps = 7500,
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.tRP_ps = 13125,
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.tRAS_ps = 37500,
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.tRC_ps = 50625,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 37500,
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};
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "Fixed DDR on board";
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if ((controller_number == 0) && (dimm_number == 0)) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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struct cpu_type *cpu;
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int i;
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popts->clk_adjust = 6;
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popts->cpo_override = 0x1f;
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popts->write_data_delay = 2;
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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popts->wrlvl_start = 0x8;
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popts->trwt_override = 1;
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popts->trwt = 0;
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cpu = gd->cpu;
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/* P1014 and it's derivatives support max 16it DDR width */
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if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
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popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
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popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
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}
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}
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#endif /* CONFIG_DDR_RAW_TIMING */
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35
board/freescale/p1010rdb/law.c
Normal file
35
board/freescale/p1010rdb/law.c
Normal file
@ -0,0 +1,35 @@
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
||||
*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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#ifndef CONFIG_SDCARD
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
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SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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330
board/freescale/p1010rdb/p1010rdb.c
Normal file
330
board/freescale/p1010rdb/p1010rdb.c
Normal file
@ -0,0 +1,330 @@
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/*
|
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
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#include <asm/processor.h>
|
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#include <asm/mmu.h>
|
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#include <asm/cache.h>
|
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#include <asm/immap_85xx.h>
|
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#include <asm/io.h>
|
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#include <miiphy.h>
|
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#include <libfdt.h>
|
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#include <fdt_support.h>
|
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#include <fsl_mdio.h>
|
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#include <tsec.h>
|
||||
#include <mmc.h>
|
||||
#include <netdev.h>
|
||||
#include <pci.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_ifc.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
|
||||
#ifndef CONFIG_SDCARD
|
||||
#include <hwconfig.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define GPIO4_PCIE_RESET_SET 0x08000000
|
||||
#define MUX_CPLD_CAN_UART 0x00
|
||||
#define MUX_CPLD_TDM 0x01
|
||||
#define MUX_CPLD_SPICS0_FLASH 0x00
|
||||
#define MUX_CPLD_SPICS0_SLIC 0x02
|
||||
|
||||
#ifndef CONFIG_SDCARD
|
||||
struct cpld_data {
|
||||
u8 cpld_ver; /* cpld revision */
|
||||
u8 pcba_ver; /* pcb revision number */
|
||||
u8 twindie_ddr3;
|
||||
u8 res1[6];
|
||||
u8 bank_sel; /* NOR Flash bank */
|
||||
u8 res2[5];
|
||||
u8 usb2_sel;
|
||||
u8 res3[1];
|
||||
u8 porsw_sel;
|
||||
u8 tdm_can_sel;
|
||||
u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
|
||||
u8 por0; /* POR Options */
|
||||
u8 por1; /* POR Options */
|
||||
u8 por2; /* POR Options */
|
||||
u8 por3; /* POR Options */
|
||||
};
|
||||
|
||||
void cpld_show(void)
|
||||
{
|
||||
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
|
||||
|
||||
printf("CPLD: V%x.%x PCBA: V%x.0\n",
|
||||
in_8(&cpld_data->cpld_ver) & 0xF0,
|
||||
in_8(&cpld_data->cpld_ver) & 0x0F,
|
||||
in_8(&cpld_data->pcba_ver) & 0x0F);
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
printf("twindie_ddr =%x\n",
|
||||
in_8(&cpld_data->twindie_ddr3));
|
||||
printf("bank_sel =%x\n",
|
||||
in_8(&cpld_data->bank_sel));
|
||||
printf("usb2_sel =%x\n",
|
||||
in_8(&cpld_data->usb2_sel));
|
||||
printf("porsw_sel =%x\n",
|
||||
in_8(&cpld_data->porsw_sel));
|
||||
printf("tdm_can_sel =%x\n",
|
||||
in_8(&cpld_data->tdm_can_sel));
|
||||
printf("tdm_can_sel =%x\n",
|
||||
in_8(&cpld_data->tdm_can_sel));
|
||||
printf("spi_cs0_sel =%x\n",
|
||||
in_8(&cpld_data->spi_cs0_sel));
|
||||
printf("bcsr0 =%x\n",
|
||||
in_8(&cpld_data->bcsr0));
|
||||
printf("bcsr1 =%x\n",
|
||||
in_8(&cpld_data->bcsr1));
|
||||
printf("bcsr2 =%x\n",
|
||||
in_8(&cpld_data->bcsr2));
|
||||
printf("bcsr3 =%x\n",
|
||||
in_8(&cpld_data->bcsr3));
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
|
||||
#ifndef CONFIG_SDCARD
|
||||
struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
|
||||
|
||||
/* Clock configuration to access CPLD using IFC(GPCM) */
|
||||
setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
|
||||
#endif
|
||||
/*
|
||||
* Reset PCIe slots via GPIO4
|
||||
*/
|
||||
setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
|
||||
setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
#ifndef CONFIG_SDCARD
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash */
|
||||
disable_tlb(flash_esel);
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_16M, 1);
|
||||
|
||||
set_tlb(1, flashbase + 0x1000000,
|
||||
CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_init_board(void)
|
||||
{
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
#endif /* ifdef CONFIG_PCI */
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
struct cpu_type *cpu;
|
||||
|
||||
cpu = gd->cpu;
|
||||
printf("Board: %sRDB ", cpu->name);
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
puts("(36-bit addrmap)");
|
||||
#endif
|
||||
puts("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct fsl_pq_mdio_info mdio_info;
|
||||
struct tsec_info_struct tsec_info[4];
|
||||
struct cpu_type *cpu;
|
||||
int num = 0;
|
||||
|
||||
cpu = gd->cpu;
|
||||
|
||||
#ifdef CONFIG_TSEC1
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC2
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 2);
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC3
|
||||
/* P1014 and it's derivatives do not support eTSEC3 */
|
||||
if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) {
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 3);
|
||||
num++;
|
||||
}
|
||||
#endif
|
||||
if (!num) {
|
||||
printf("No TSECs initialized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
|
||||
mdio_info.name = DEFAULT_MII_NAME;
|
||||
|
||||
fsl_pq_mdio_init(bis, &mdio_info);
|
||||
|
||||
tsec_eth_init(bis, tsec_info, num);
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void fdt_del_flexcan(void *blob)
|
||||
{
|
||||
int nodeoff = 0;
|
||||
|
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
|
||||
"fsl,flexcan-v1.0")) >= 0) {
|
||||
fdt_del_node(blob, nodeoff);
|
||||
}
|
||||
}
|
||||
|
||||
void fdt_del_spi_flash(void *blob)
|
||||
{
|
||||
int nodeoff = 0;
|
||||
|
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
|
||||
"spansion,s25sl12801")) >= 0) {
|
||||
fdt_del_node(blob, nodeoff);
|
||||
}
|
||||
}
|
||||
|
||||
void fdt_del_spi_slic(void *blob)
|
||||
{
|
||||
int nodeoff = 0;
|
||||
|
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
|
||||
"zarlink,le88266")) >= 0) {
|
||||
fdt_del_node(blob, nodeoff);
|
||||
}
|
||||
}
|
||||
|
||||
void fdt_del_tdm(void *blob)
|
||||
{
|
||||
int nodeoff = 0;
|
||||
|
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
|
||||
"fsl,starlite-tdm")) >= 0) {
|
||||
fdt_del_node(blob, nodeoff);
|
||||
}
|
||||
}
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
struct cpu_type *cpu;
|
||||
|
||||
cpu = gd->cpu;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
FT_FSL_PCI_SETUP;
|
||||
#endif
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
fdt_fixup_dr_usb(blob, bd);
|
||||
|
||||
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
|
||||
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
|
||||
fdt_del_flexcan(blob);
|
||||
fdt_del_node_and_alias(blob, "ethernet2");
|
||||
}
|
||||
#ifndef CONFIG_SDCARD
|
||||
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
|
||||
printf("fdt CAN");
|
||||
fdt_del_tdm(blob);
|
||||
fdt_del_spi_slic(blob);
|
||||
}
|
||||
#ifndef CONFIG_SPIFLASH
|
||||
else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
|
||||
printf("fdt TDM");
|
||||
fdt_del_flexcan(blob);
|
||||
fdt_del_spi_flash(blob);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SDCARD
|
||||
int misc_init_r(void)
|
||||
{
|
||||
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
|
||||
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
|
||||
MPC85xx_PMUXCR_CAN1_UART |
|
||||
MPC85xx_PMUXCR_CAN2_TDM |
|
||||
MPC85xx_PMUXCR_CAN2_UART);
|
||||
out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
|
||||
}
|
||||
#ifndef CONFIG_SPIFLASH
|
||||
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
|
||||
printf("TDM");
|
||||
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
|
||||
MPC85xx_PMUXCR_CAN1_UART);
|
||||
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
|
||||
MPC85xx_PMUXCR_CAN1_TDM);
|
||||
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
|
||||
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
|
||||
out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
|
||||
out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
98
board/freescale/p1010rdb/tlb.c
Normal file
98
board/freescale/p1010rdb/tlb.c
Normal file
@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#ifndef CONFIG_SDCARD
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
|
||||
CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SDCARD
|
||||
/* *I*G - Board CPLD */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 8, BOOKE_PAGESZ_1G, 1)
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -567,6 +567,12 @@ MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freesca
|
||||
MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
|
||||
MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
|
||||
MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
|
||||
P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB
|
||||
P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT
|
||||
P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD
|
||||
P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH
|
||||
P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD
|
||||
P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH
|
||||
P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB
|
||||
P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT
|
||||
P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD
|
||||
|
||||
706
include/configs/P1010RDB.h
Normal file
706
include/configs/P1010RDB.h
Normal file
@ -0,0 +1,706 @@
|
||||
/*
|
||||
* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* P010 RDB board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_36BIT
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_P1010RDB
|
||||
#define CONFIG_P1010
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_RAMBOOT_SDCARD
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11000000
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPIFLASH
|
||||
#define CONFIG_RAMBOOT_SPIFLASH
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11000000
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE /* BOOKE */
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
|
||||
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#define CONFIG_E1000 /* E1000 pci Ethernet card*/
|
||||
|
||||
/*
|
||||
* PCI Windows
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
/* controller 1, Slot 1, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
|
||||
#endif
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_TSEC_ENET
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
|
||||
|
||||
#ifndef CONFIG_SDCARD
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#endif
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP 1
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_FSL_DDR3
|
||||
#define CONFIG_DDR_RAW_TIMING
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
#define SPD_EEPROM_ADDRESS 0x52
|
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_sdram_size(void);
|
||||
#endif
|
||||
#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
|
||||
/* DDR3 Controller Settings */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
|
||||
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_1 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 0x04401010
|
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
|
||||
#define CONFIG_SYS_DDR_TIMING_5 0x03402400
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
|
||||
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
|
||||
#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
|
||||
#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
|
||||
#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
|
||||
#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
|
||||
|
||||
/* settings for DDR3 at 667MT/s */
|
||||
#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
|
||||
#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
|
||||
#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
|
||||
#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
|
||||
#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
|
||||
#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x3fff_ffff DDR 1G cacheable
|
||||
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
|
||||
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
|
||||
*
|
||||
* Localbus non-cacheable
|
||||
* 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
|
||||
* 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
|
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
|
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
||||
*/
|
||||
|
||||
/* In case of SD card boot, IFC interface is not available because of muxing */
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#else
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
/* NOR Flash on IFC */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xee000000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5)
|
||||
#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x0f)
|
||||
#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWP(0x1c)
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
/* CFI for NOR Flash */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_NAND \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
|
||||
| CSOR_NAND_PGS_512 /* Page Size = 512b */ \
|
||||
| CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
|
||||
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
|
||||
|
||||
/* NAND Flash Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
|
||||
FTIM0_NAND_TWP(0x0C) | \
|
||||
FTIM0_NAND_TWCHT(0x04) | \
|
||||
FTIM0_NAND_TWH(0x05)
|
||||
#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
|
||||
FTIM1_NAND_TWBE(0x1d) | \
|
||||
FTIM1_NAND_TRR(0x07) | \
|
||||
FTIM1_NAND_TRP(0x0c)
|
||||
#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
|
||||
FTIM2_NAND_TREH(0x05) | \
|
||||
FTIM2_NAND_TWHRE(0x0f)
|
||||
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
|
||||
/* Set up IFC registers for boot location NOR/NAND */
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
|
||||
/* CPLD on IFC */
|
||||
#define CONFIG_SYS_CPLD_BASE 0xffb00000
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_CSOR3 0x0
|
||||
/* CPLD Timing parameters for IFC CS3 */
|
||||
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x0) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS3_FTIM3 0x0
|
||||
#endif /* CONFIG_SDCARD */
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
|
||||
defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C EEPROM */
|
||||
#undef CONFIG_ID_EEPROM
|
||||
/* enable read and write access to EEPROM */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_RTC_PT7C4338
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
/*
|
||||
* SPI interface will not be available in case of NAND boot SPI CS0 will be
|
||||
* used for SLIC
|
||||
*/
|
||||
/* eSPI - Enhanced SPI */
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
#define CONFIG_TSEC3 1
|
||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
||||
|
||||
#define TSEC1_PHY_ADDR 1
|
||||
#define TSEC2_PHY_ADDR 0
|
||||
#define TSEC3_PHY_ADDR 2
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC3_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
|
||||
/* TBI PHY configuration for SGMII mode */
|
||||
#define CONFIG_TSEC_TBICR_SETTINGS ( \
|
||||
TBICR_PHY_RESET \
|
||||
| TBICR_ANEG_ENABLE \
|
||||
| TBICR_FULL_DUPLEX \
|
||||
| TBICR_SPEED1_SET \
|
||||
)
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_FSL_SATA
|
||||
#define CONFIG_LIBATA
|
||||
|
||||
#ifdef CONFIG_FSL_SATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
#define CONFIG_SATA2
|
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
|
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
||||
|
||||
#define CONFIG_CMD_SATA
|
||||
#define CONFIG_LBA48
|
||||
#endif /* #ifdef CONFIG_FSL_SATA */
|
||||
|
||||
/* SD interface will only be available in case of SD boot */
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_DEF_HWCONFIG esdhc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#endif
|
||||
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB)
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_SDCARD)
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
|
||||
|| defined(CONFIG_FSL_SATA)
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#endif
|
||||
|
||||
#define CONFIG_HOSTNAME P1010RDB
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=p1010rdb.dtb\0" \
|
||||
"bdev=sda1\0" \
|
||||
"hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
|
||||
"othbootargs=ramdisk_size=600000\0" \
|
||||
"usbfatboot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"fatload usb 0:2 $loadaddr $bootfile;" \
|
||||
"fatload usb 0:2 $fdtaddr $fdtfile;" \
|
||||
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
"usbext2boot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
x
Reference in New Issue
Block a user