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x86: ivybridge: Use reset_cpu()

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Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2015-04-28 20:11:30 -06:00
parent ff6a8f3c06
commit 5021c81faa
3 changed files with 6 additions and 15 deletions
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5
arch/x86/cpu/ivybridge/cpu.c
View File

@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void)
/* Issue warm reset, will be "CPU only" due to soft reset data */ /* Issue warm reset, will be "CPU only" due to soft reset data */
outb(0x0, PORT_RESET); outb(0x0, PORT_RESET);
outb(0x6, PORT_RESET); outb(SYS_RST | RST_CPU, PORT_RESET);
cpu_hlt(); cpu_hlt();
/* Not reached */ /* Not reached */
@ -286,8 +286,7 @@ int print_cpuinfo(void)
/* System is not happy after keyboard reset... */ /* System is not happy after keyboard reset... */
debug("Issuing CF9 warm reset\n"); debug("Issuing CF9 warm reset\n");
outb(0x6, 0xcf9); reset_cpu(0);
cpu_hlt();
} }
/* Early chipset init required before RAM init can work */ /* Early chipset init required before RAM init can work */

13
arch/x86/cpu/ivybridge/early_me.c
View File

@ -117,7 +117,6 @@ static inline void set_global_reset(int enable)
int intel_early_me_init_done(u8 status) int intel_early_me_init_done(u8 status)
{ {
u8 reset;
int count; int count;
u32 mebase_l, mebase_h; u32 mebase_l, mebase_h;
struct me_hfs hfs; struct me_hfs hfs;
@ -156,7 +155,6 @@ int intel_early_me_init_done(u8 status)
/* Check status after acknowledgement */ /* Check status after acknowledgement */
intel_early_me_status(); intel_early_me_status();
reset = 0;
switch (hfs.ack_data) { switch (hfs.ack_data) {
case ME_HFS_ACK_CONTINUE: case ME_HFS_ACK_CONTINUE:
/* Continue to boot */ /* Continue to boot */
@ -164,17 +162,17 @@ int intel_early_me_init_done(u8 status)
case ME_HFS_ACK_RESET: case ME_HFS_ACK_RESET:
/* Non-power cycle reset */ /* Non-power cycle reset */
set_global_reset(0); set_global_reset(0);
reset = 0x06; reset_cpu(0);
break; break;
case ME_HFS_ACK_PWR_CYCLE: case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */ /* Power cycle reset */
set_global_reset(0); set_global_reset(0);
reset = 0x0e; x86_full_reset();
break; break;
case ME_HFS_ACK_GBL_RESET: case ME_HFS_ACK_GBL_RESET:
/* Global reset */ /* Global reset */
set_global_reset(1); set_global_reset(1);
reset = 0x0e; x86_full_reset();
break; break;
case ME_HFS_ACK_S3: case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4: case ME_HFS_ACK_S4:
@ -182,10 +180,5 @@ int intel_early_me_init_done(u8 status)
break; break;
} }
/* Perform the requested reset */
if (reset) {
outb(reset, 0xcf9);
cpu_hlt();
}
return -1; return -1;
} }

3
arch/x86/cpu/ivybridge/sdram.c
View File

@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data)
/* If MRC data is not found we cannot continue S3 resume. */ /* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
debug("Giving up in sdram_initialize: No MRC data\n"); debug("Giving up in sdram_initialize: No MRC data\n");
outb(0x6, PORT_RESET); reset_cpu(0);
cpu_hlt();
} }
/* Pass console handler in pei_data */ /* Pass console handler in pei_data */