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Merge branch '2022-12-21-CONFIG-migration-work' into next

Browse Source 
- Bring in the second to last big batch of CONFIG migrations and
  renames. Of note here we fix a few inconsistencies around the baudrate
  tables on some SoCs and now are consistent in hostname/etc handling in
  the environment.
This commit is contained in:
Tom Rini 2022-12-22 10:33:04 -05:00
commit 52d91e1c20
633 changed files with 1228 additions and 5682 deletions
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98
README
View File

@ -373,12 +373,6 @@ The following options need to be configured:
such as ARM architectural timer initialization.
- Linux Kernel Interface:
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
When transferring memsize parameter to Linux, some versions
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
CONFIG_OF_LIBFDT
New kernel versions are expecting firmware settings to be
@ -585,11 +579,6 @@ The following options need to be configured:
Support for generic parallel port TPM devices. Only one device
per system is supported at this time.
CONFIG_TPM_TIS_BASE_ADDRESS
Base address where the generic TPM device is mapped
to. Contemporary x86 systems usually map it at
0xfed40000.
CONFIG_TPM
Define this to enable the TPM support library which provides
functional interfaces to some TPM commands.
@ -629,14 +618,6 @@ The following options need to be configured:
variable usbtty to be cdc_acm should suffice. The following
might be defined in YourBoardName.h
CONFIG_USBD_HS
Define this to enable the high speed support for usb
device and usbtty. If this feature is enabled, a routine
int is_usbd_high_speed(void)
also needs to be defined by the driver to dynamically poll
whether the enumeration has succeded at high speed or full
speed.
If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
or directly in usbd_vendor_info.h. If you don't define
@ -734,38 +715,6 @@ The following options need to be configured:
Some PHY like Intel LXT971A need extra delay after
command issued before MII status register can be read
- IP address:
CONFIG_IPADDR
Define a default value for the IP address to use for
the default Ethernet interface, in case this is not
determined through e.g. bootp.
(Environment variable "ipaddr")
- Server IP address:
CONFIG_SERVERIP
Defines a default value for the IP address of a TFTP
server to contact when using the "tftboot" command.
(Environment variable "serverip")
- Gateway IP address:
CONFIG_GATEWAYIP
Defines a default value for the IP address of the
default router where packets to other networks are
sent to.
(Environment variable "gatewayip")
- Subnet mask:
CONFIG_NETMASK
Defines a default value for the subnet mask (or
routing prefix) which is used to determine if an IP
address belongs to the local subnet or needs to be
forwarded through a router.
(Environment variable "netmask")
- BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY
@ -1016,21 +965,13 @@ The following options need to be configured:
CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
is set, specify a list of bus-device pairs. Otherwise, specify
a 1D array of device addresses
when the 'i2c probe' command is issued.
e.g.
#undef CONFIG_I2C_MULTI_BUS
#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
#define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
CFG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
@ -1122,13 +1063,6 @@ The following options need to be configured:
completely disabled. Anybody can change or delete
these parameters.
Alternatively, if you define _both_ an ethaddr in the
default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
Ethernet address is installed in the environment,
which can be changed exactly ONCE by the user. [The
serial# is unaffected by this, i. e. it remains
read-only.]
The same can be accomplished in a more flexible way
for any variable by configuring the type of access
to allow for those variables in the ".flags" variable
@ -1224,13 +1158,6 @@ The following options need to be configured:
this is instead controlled by the value of
/config/load-environment.
CONFIG_STANDALONE_LOAD_ADDR
This option defines a board specific value for the
address where standalone program gets loaded, thus
overwriting the architecture dependent default
settings.
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
@ -1477,24 +1404,6 @@ Configuration Settings:
- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash.
- CONFIG_FLASH_SPANSION_S29WS_N
s29ws-n MirrorBit flash has non-standard addresses for buffered
write commands.
- CONFIG_FLASH_SHOW_PROGRESS
If defined (must be an integer), print out countdown
digits and dots. Recommended value: 45 (9..1) for 80
column displays, 15 (3..1) for 40 column displays.
- CONFIG_FLASH_VERIFY
If defined, the content of the flash (destination) is compared
against the source after the write operation. An error message
will be printed when the contents are not identical.
Please note that this option is useless in nearly all cases,
since such flash programming errors usually are detected earlier
while unprotecting/erasing/programming. Please only enable
this option if you really know what you are doing.
- CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when
@ -1542,11 +1451,6 @@ The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
following configurations:
- CONFIG_BUILD_ENVCRC:
Builds up envcrc with the target environment so that external utils
may easily extract it and embed it in final U-Boot images.
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or

19
api/Kconfig
View File

@ -11,3 +11,22 @@ config SYS_MMC_MAX_DEVICE
default 1
endmenu
config STANDALONE_LOAD_ADDR
hex "Address in memory to link standalone applications to"
default 0xffffffff80200000 if MIPS && 64BIT
default 0x8c000000 if SH
default 0x82000000 if ARC
default 0x80f00000 if MICROBLAZE
default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
default 0x80200000 if MIPS && 32BIT
default 0x0c100000 if ARM
default 0x02000000 if NIOS2
default 0x00040000 if PPC || X86
default 0x00020000 if M68K
default 0x0 if RISCV
default SYS_LOAD_ADDR
help
This option defines a board specific value for the address where
standalone program gets loaded, thus overwriting the architecture
dependent default settings.

4
arch/Kconfig
View File

@ -380,6 +380,10 @@ config SYS_IMMR
Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of many Freescale / NXP SoCs.
config MONITOR_IS_IN_RAM
bool "U-Boot is loaded in to RAM by a pre-loader"
depends on M68K || NIOS2
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on ARM || MIPS || RISCV

17
arch/Kconfig.nxp
View File

@ -1,5 +1,10 @@
config FSL_TRUST_ARCH_v1
bool
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
ARCH_P5040 || ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
@ -10,6 +15,7 @@ menu "Chain of trust / secure boot options"
config CHAIN_OF_TRUST
select FSL_CAAM
select ARCH_MISC_INIT
select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
select FSL_SEC_MON
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
@ -41,6 +47,17 @@ config ESBC_ADDR_64BIT
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
config FSL_ISBC_KEY_EXT
bool
help
The key used for verification of next level images is picked up from
an Extension Table which has been verified by the ISBC (Internal
Secure boot Code) in boot ROM of the SoC. The feature is only
applicable in case of NOR boot and is not applicable in case of
RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
for all device if IE Table is copied to XIP memory Also, for
Layerscape, ISBC doesn't verify this table.
config SYS_FSL_SFP_BE
def_bool y
depends on PPC || FSL_LSCH2 || ARCH_LS1021A

3
arch/arc/config.mk
View File

@ -21,6 +21,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
# Needed for relocation
LDFLAGS_FINAL += -pie --gc-sections
# Load address for standalone apps
CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000

5
arch/arm/Kconfig
View File

@ -915,6 +915,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@ -928,6 +929,7 @@ config ARCH_MX6
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@ -1597,6 +1599,7 @@ config TARGET_LS1021AQDS
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
@ -1615,6 +1618,7 @@ config TARGET_LS1021ATWR
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
@ -1679,6 +1683,7 @@ config TARGET_LS1021AIOT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER

8
arch/arm/config.mk
View File

@ -3,14 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar

3
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -51,6 +51,9 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config PEN_ADDR_BIG_ENDIAN
bool
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400

9
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -302,15 +302,6 @@ int cpu_mmc_init(struct bd_info *bis)
}
#endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif
return 0;
}
int arch_cpu_init(void)
{
void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);

3
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1057,9 +1057,6 @@ int cpu_eth_init(struct bd_info *bis)
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif
return error;
}

2
arch/arm/include/asm/arch-am33xx/clock.h
View File

@ -13,7 +13,7 @@
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
#if defined(CONFIG_TI816X)
#include <asm/arch/clock_ti81xx.h>
#endif

36
arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
View File

@ -44,9 +44,7 @@ struct cm_alwon {
unsigned int mmu_clkstctrl;
unsigned int mmucfg_clkstctrl;
unsigned int ocmc0clkstctrl;
#if defined(CONFIG_TI814X)
unsigned int vcpclkstctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int ocmc1clkstctrl;
#endif
unsigned int mpuclkstctrl;
@ -67,16 +65,7 @@ struct cm_alwon {
unsigned int gpio1clkctrl;
unsigned int i2c0clkctrl;
unsigned int i2c1clkctrl;
#if defined(CONFIG_TI814X)
unsigned int mcasp345clkctrl;
unsigned int atlclkctrl;
unsigned int mlbclkctrl;
unsigned int pataclkctrl;
unsigned int resv1[1];
unsigned int uart3clkctrl;
unsigned int uart4clkctrl;
unsigned int uart5clkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int resv1[1];
unsigned int timer1clkctrl;
unsigned int timer2clkctrl;
@ -93,16 +82,12 @@ struct cm_alwon {
unsigned int mmudataclkctrl;
unsigned int resv2[2];
unsigned int mmucfgclkctrl;
#if defined(CONFIG_TI814X)
unsigned int resv3[2];
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int resv3[1];
unsigned int sdioclkctrl;
#endif
unsigned int ocmc0clkctrl;
#if defined(CONFIG_TI814X)
unsigned int vcpclkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int ocmc1clkctrl;
#endif
unsigned int resv4[2];
@ -112,9 +97,7 @@ struct cm_alwon {
unsigned int ethernet0clkctrl;
unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
#if defined(CONFIG_TI814X)
unsigned int debugssclkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int resv6[1];
#endif
unsigned int l3clkctrl;
@ -126,14 +109,7 @@ struct cm_alwon {
unsigned int tptc1clkctrl;
unsigned int tptc2clkctrl;
unsigned int tptc3clkctrl;
#if defined(CONFIG_TI814X)
unsigned int resv6[4];
unsigned int dcan01clkctrl;
unsigned int mmchs0clkctrl;
unsigned int mmchs1clkctrl;
unsigned int mmchs2clkctrl;
unsigned int custefuseclkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int sr0clkctrl;
unsigned int sr1clkctrl;
#endif

2
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@ -16,8 +16,6 @@
#include <asm/arch/hardware_am33xx.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/hardware_ti816x.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/hardware_ti814x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/hardware_am43xx.h>
#endif

60
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
View File

@ -1,60 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* hardware_ti814x.h
*
* TI814x hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_TI814X_H
#define __AM33XX_HARDWARE_TI814X_H
/* Module base addresses */
/* UART Base Address */
#define UART0_BASE 0x48020000
/* Watchdog Timer */
#define WDT_BASE 0x481C7000
/* Control Module Base Address */
#define CTRL_BASE 0x48140000
#define CTRL_DEVICE_BASE 0x48140600
/* PRCM Base Address */
#define PRCM_BASE 0x48180000
#define CM_PER 0x44E00000
#define CM_WKUP 0x44E00400
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
#define PRM_RSTST (PRM_RSTCTRL + 8)
/* PLL Subsystem Base Address */
#define PLL_SUBSYS_BASE 0x481C5000
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x48140E0C
#define VTP1_CTRL_ADDR 0x48140E10
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x47C0C400
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
#define DDR_PHY_CMD_ADDR2 0x47C0C800
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 4
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A100800
/* RTC base address */
#define RTC_BASE 0x480C0000
/* OTG */
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
#endif /* __AM33XX_HARDWARE_TI814X_H */

5
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
View File

@ -24,10 +24,7 @@
#define OMAP_HSMMC1_BASE 0x48060000
#define OMAP_HSMMC2_BASE 0x481D8000
#if defined(CONFIG_TI814X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 192 /* MHz */
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 48 /* MHz */
#endif

2
arch/arm/include/asm/arch-am33xx/mux.h
View File

@ -20,8 +20,6 @@
#ifdef CONFIG_AM33XX
#include <asm/arch/mux_am33xx.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/mux_ti814x.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/mux_ti816x.h>
#elif defined(CONFIG_AM43XX)

311
arch/arm/include/asm/arch-am33xx/mux_ti814x.h
View File

@ -1,311 +0,0 @@
/*
* mux_ti814x.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MUX_TI814X_H_
#define _MUX_TI814X_H_
/* PAD Control Fields */
#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */
#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */
#define PULLUDEN (0x0 << 16) /* Pull up enabled */
#define PULLUDDIS (0x1 << 16) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
#define MUX_CFG(value, offset) \
{ \
int tmp; \
tmp = __raw_readl(CTRL_BASE + offset); \
tmp &= PINCNTL_RSV_MSK; \
__raw_writel(tmp | value, (CTRL_BASE + offset));\
}
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int pincntl1;
int pincntl2;
int pincntl3;
int pincntl4;
int pincntl5;
int pincntl6;
int pincntl7;
int pincntl8;
int pincntl9;
int pincntl10;
int pincntl11;
int pincntl12;
int pincntl13;
int pincntl14;
int pincntl15;
int pincntl16;
int pincntl17;
int pincntl18;
int pincntl19;
int pincntl20;
int pincntl21;
int pincntl22;
int pincntl23;
int pincntl24;
int pincntl25;
int pincntl26;
int pincntl27;
int pincntl28;
int pincntl29;
int pincntl30;
int pincntl31;
int pincntl32;
int pincntl33;
int pincntl34;
int pincntl35;
int pincntl36;
int pincntl37;
int pincntl38;
int pincntl39;
int pincntl40;
int pincntl41;
int pincntl42;
int pincntl43;
int pincntl44;
int pincntl45;
int pincntl46;
int pincntl47;
int pincntl48;
int pincntl49;
int pincntl50;
int pincntl51;
int pincntl52;
int pincntl53;
int pincntl54;
int pincntl55;
int pincntl56;
int pincntl57;
int pincntl58;
int pincntl59;
int pincntl60;
int pincntl61;
int pincntl62;
int pincntl63;
int pincntl64;
int pincntl65;
int pincntl66;
int pincntl67;
int pincntl68;
int pincntl69;
int pincntl70;
int pincntl71;
int pincntl72;
int pincntl73;
int pincntl74;
int pincntl75;
int pincntl76;
int pincntl77;
int pincntl78;
int pincntl79;
int pincntl80;
int pincntl81;
int pincntl82;
int pincntl83;
int pincntl84;
int pincntl85;
int pincntl86;
int pincntl87;
int pincntl88;
int pincntl89;
int pincntl90;
int pincntl91;
int pincntl92;
int pincntl93;
int pincntl94;
int pincntl95;
int pincntl96;
int pincntl97;
int pincntl98;
int pincntl99;
int pincntl100;
int pincntl101;
int pincntl102;
int pincntl103;
int pincntl104;
int pincntl105;
int pincntl106;
int pincntl107;
int pincntl108;
int pincntl109;
int pincntl110;
int pincntl111;
int pincntl112;
int pincntl113;
int pincntl114;
int pincntl115;
int pincntl116;
int pincntl117;
int pincntl118;
int pincntl119;
int pincntl120;
int pincntl121;
int pincntl122;
int pincntl123;
int pincntl124;
int pincntl125;
int pincntl126;
int pincntl127;
int pincntl128;
int pincntl129;
int pincntl130;
int pincntl131;
int pincntl132;
int pincntl133;
int pincntl134;
int pincntl135;
int pincntl136;
int pincntl137;
int pincntl138;
int pincntl139;
int pincntl140;
int pincntl141;
int pincntl142;
int pincntl143;
int pincntl144;
int pincntl145;
int pincntl146;
int pincntl147;
int pincntl148;
int pincntl149;
int pincntl150;
int pincntl151;
int pincntl152;
int pincntl153;
int pincntl154;
int pincntl155;
int pincntl156;
int pincntl157;
int pincntl158;
int pincntl159;
int pincntl160;
int pincntl161;
int pincntl162;
int pincntl163;
int pincntl164;
int pincntl165;
int pincntl166;
int pincntl167;
int pincntl168;
int pincntl169;
int pincntl170;
int pincntl171;
int pincntl172;
int pincntl173;
int pincntl174;
int pincntl175;
int pincntl176;
int pincntl177;
int pincntl178;
int pincntl179;
int pincntl180;
int pincntl181;
int pincntl182;
int pincntl183;
int pincntl184;
int pincntl185;
int pincntl186;
int pincntl187;
int pincntl188;
int pincntl189;
int pincntl190;
int pincntl191;
int pincntl192;
int pincntl193;
int pincntl194;
int pincntl195;
int pincntl196;
int pincntl197;
int pincntl198;
int pincntl199;
int pincntl200;
int pincntl201;
int pincntl202;
int pincntl203;
int pincntl204;
int pincntl205;
int pincntl206;
int pincntl207;
int pincntl208;
int pincntl209;
int pincntl210;
int pincntl211;
int pincntl212;
int pincntl213;
int pincntl214;
int pincntl215;
int pincntl216;
int pincntl217;
int pincntl218;
int pincntl219;
int pincntl220;
int pincntl221;
int pincntl222;
int pincntl223;
int pincntl224;
int pincntl225;
int pincntl226;
int pincntl227;
int pincntl228;
int pincntl229;
int pincntl230;
int pincntl231;
int pincntl232;
int pincntl233;
int pincntl234;
int pincntl235;
int pincntl236;
int pincntl237;
int pincntl238;
int pincntl239;
int pincntl240;
int pincntl241;
int pincntl242;
int pincntl243;
int pincntl244;
int pincntl245;
int pincntl246;
int pincntl247;
int pincntl248;
int pincntl249;
int pincntl250;
int pincntl251;
int pincntl252;
int pincntl253;
int pincntl254;
int pincntl255;
int pincntl256;
int pincntl257;
int pincntl258;
int pincntl259;
int pincntl260;
int pincntl261;
int pincntl262;
int pincntl263;
int pincntl264;
int pincntl265;
int pincntl266;
int pincntl267;
int pincntl268;
int pincntl269;
int pincntl270;
};
#endif /* endif _MUX_TI814X_H_ */

2
arch/arm/include/asm/arch-am33xx/omap.h
View File

@ -20,7 +20,7 @@
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define NON_SECURE_SRAM_IMG_END 0x4030B800
#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
#elif defined(CONFIG_TI816X)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define NON_SECURE_SRAM_IMG_END 0x4031B800

16
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -9,21 +9,7 @@
#define BOOT_DEVICE_NONE 0x00
#define BOOT_DEVICE_MMC2_2 0xFF
#if defined(CONFIG_TI814X)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x05
#define BOOT_DEVICE_NAND_I2C 0x06
#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */
#define BOOT_DEVICE_MMC1 0x09
#define BOOT_DEVICE_SPI 0x15
#define BOOT_DEVICE_UART 0x41
#define BOOT_DEVICE_USBETH 0x44
#define BOOT_DEVICE_CPGMAC 0x46
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x03

2
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -14,8 +14,6 @@
#include <linux/bitops.h>
#endif
#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
/*
* Reserve secure memory
* To be aligned with MMU block size

1
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -70,7 +70,6 @@
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#ifdef CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif

15
arch/arm/include/asm/fsl_secure_boot.h
View File

@ -9,21 +9,6 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
* is picked up from an Extension Table which has
* been verified by the ISBC (Internal Secure boot Code)
* in boot ROM of the SoC.
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
* For LS, this feature is available for all device if IE Table
* is copied to XIP memory
* Also, for LS, ISBC doesn't verify this table.
*/
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
#ifdef CONFIG_FSL_LS_PPA
/* Define the key hash here if SRK used for signing PPA image is
* different from SRK hash put in SFP used for U-Boot.

8
arch/arm/mach-exynos/Kconfig
View File

@ -4,6 +4,12 @@ config BOARD_COMMON
def_bool y
depends on !TARGET_SMDKV310 && !TARGET_ARNDALE
config SPI_BOOTING
bool
config USB_BOOTING
bool
choice
prompt "EXYNOS architecture type select"
optional
@ -24,6 +30,8 @@ config ARCH_EXYNOS5
select BOARD_EARLY_INIT_F
select CPU_V7A
select SHA_HW_ACCEL
select SPI_BOOTING if EXYNOS5_DT
select USB_BOOTING
imply CMD_HASH
imply CRC32_VERIFY
imply HASH_VERIFY

3
arch/arm/mach-imx/Kconfig
View File

@ -18,6 +18,9 @@ config SYSCOUNTER_TIMER
config GPT_TIMER
bool
config MXC_GPT_HCLK
bool
config IMX_RDC
bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7

9
arch/arm/mach-mvebu/include/mach/config.h
View File

@ -30,13 +30,4 @@
/* Needed for SPI NOR booting in SPL */
#define CONFIG_DM_SEQ_ALIAS 1
/*
* I2C related stuff
*/
#ifdef CONFIG_CMD_I2C
#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_I2C_MVTWSI
#endif
#endif
#endif /* __MVEBU_CONFIG_H */

8
arch/arm/mach-omap2/Kconfig
View File

@ -75,14 +75,6 @@ config OMAP54XX
imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
config TI814X
bool "TI814X SoC"
select SPECIFY_CONSOLE_INDEX
help
Support for AM335x SOC from Texas Instruments.
The AM335x high performance SOC features a Cortex-A8
ARM core and more.
config TI816X
bool "TI816X SoC"
select SPECIFY_CONSOLE_INDEX

10
arch/arm/mach-omap2/am33xx/Kconfig
View File

@ -8,16 +8,6 @@ config TARGET_TI816X_EVM
endif
if TI814X
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
help
This option specifies support for the TI8148
EVM development platform.
endif
if AM33XX
config AM33XX_CHILISOM

1
arch/arm/mach-omap2/am33xx/Makefile
View File

@ -3,7 +3,6 @@
# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
obj-$(CONFIG_AM33XX) += clock_am33xx.o
obj-$(CONFIG_TI814X) += clock_ti814x.o
obj-$(CONFIG_AM43XX) += clock_am43xx.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)

410
arch/arm/mach-omap2/am33xx/clock_ti814x.c
View File

@ -1,410 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* clock_ti814x.c
*
* Clocks for TI814X based boards
*
* Copyright (C) 2013, Texas Instruments, Incorporated
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <linux/delay.h>
/* PRCM */
#define PRCM_MOD_EN 0x2
/* CLK_SRC */
#define OSC_SRC0 0
#define OSC_SRC1 1
#define L3_OSC_SRC OSC_SRC0
#define OSC_0_FREQ 20
#define DCO_HS2_MIN 500
#define DCO_HS2_MAX 1000
#define DCO_HS1_MIN 1000
#define DCO_HS1_MAX 2000
#define SELFREQDCO_HS2 0x00000801
#define SELFREQDCO_HS1 0x00001001
#define MPU_N 0x1
#define MPU_M 0x3C
#define MPU_M2 1
#define MPU_CLKCTRL 0x1
#define L3_N 19
#define L3_M 880
#define L3_M2 4
#define L3_CLKCTRL 0x801
#define DDR_N 19
#define DDR_M 666
#define DDR_M2 2
#define DDR_CLKCTRL 0x801
/* ADPLLJ register values */
#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
ADPLLJ_CLKCTRL_CLKOUTEN | \
ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
ADPLLJ_STATUS_FREQLOCK)
#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
#define ADPLLJ_STATUS_BYPASS (1 << 0)
#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
ADPLLJ_STATUS_BYPASS)
#define ADPLLJ_TENABLE_ENB (1 << 0)
#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
#define ADPLLJ_M2NDIV_M2SHIFT 16
#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
struct ad_pll {
unsigned int pwrctrl;
unsigned int clkctrl;
unsigned int tenable;
unsigned int tenablediv;
unsigned int m2ndiv;
unsigned int mn2div;
unsigned int fracdiv;
unsigned int bwctrl;
unsigned int fracctrl;
unsigned int status;
unsigned int m3div;
unsigned int rampctrl;
};
#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
#define ENET_CLKCTRL_CMPL 0x30000
#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
struct sata_pll {
unsigned int pllcfg0;
unsigned int pllcfg1;
unsigned int pllcfg2;
unsigned int pllcfg3;
unsigned int pllcfg4;
unsigned int pllstatus;
unsigned int rxstatus;
unsigned int txstatus;
unsigned int testcfg;
};
#define SEL_IN_FREQ (0x1 << 31)
#define DIGCLRZ (0x1 << 30)
#define ENDIGLDO (0x1 << 4)
#define APLL_CP_CURR (0x1 << 3)
#define ENBGSC_REF (0x1 << 2)
#define ENPLLLDO (0x1 << 1)
#define ENPLL (0x1 << 0)
#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
ENPLLLDO | ENPLL)
#define PLL_LOCK (0x1 << 0)
#define ENSATAMODE (0x1 << 31)
#define PLLREFSEL (0x1 << 30)
#define MDIVINT (0x4b << 18)
#define EN_CLKAUX (0x1 << 5)
#define EN_CLK125M (0x1 << 4)
#define EN_CLK100M (0x1 << 3)
#define EN_CLK50M (0x1 << 2)
#define SATA_PLLCFG1 (ENSATAMODE | \
PLLREFSEL | \
MDIVINT | \
EN_CLKAUX | \
EN_CLK125M | \
EN_CLK100M | \
EN_CLK50M)
#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
#define PLLDO_EN_LDO_STABLE (0x1 << 11)
#define PLLDO_EN_BUF_CUR (0x1 << 7)
#define PLLDO_EN_LP (0x1 << 6)
#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
PLLDO_EN_LDO_STABLE | \
PLLDO_EN_BUF_CUR | \
PLLDO_EN_LP | \
PLLDO_CTRL_TRIM_1_4V)
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
/*
* Enable the peripheral clock for required peripherals
*/
static void enable_per_clocks(void)
{
/* HSMMC1 */
writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
;
/* Ethernet */
writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
;
writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
;
/* RTC clocks */
writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
;
}
/*
* select the HS1 or HS2 for DCO Freq
* return : CLKCTRL
*/
static u32 pll_dco_freq_sel(u32 clkout_dco)
{
if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
return SELFREQDCO_HS2;
else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
return SELFREQDCO_HS1;
else
return -1;
}
/*
* select the sigma delta config
* return: sigma delta val
*/
static u32 pll_sigma_delta_val(u32 clkout_dco)
{
u32 sig_val = 0;
sig_val = (clkout_dco + 225) / 250;
sig_val = sig_val << 24;
return sig_val;
}
/*
* configure individual ADPLLJ
*/
static void pll_config(u32 base, u32 n, u32 m, u32 m2,
u32 clkctrl_val, int adpllj)
{
const struct ad_pll *adpll = (struct ad_pll *)base;
u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
u32 sig_val = 0, hs_mod = 0;
m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
mn2val = m;
/* calculate clkout_dco */
clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
/* sigma delta & Hs mode selection skip for ADPLLS*/
if (adpllj) {
sig_val = pll_sigma_delta_val(clkout_dco);
hs_mod = pll_dco_freq_sel(clkout_dco);
}
/* by-pass pll */
read_clkctrl = readl(&adpll->clkctrl);
writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
!= ADPLLJ_STATUS_BYPASSANDACK)
;
/* clear TINITZ */
read_clkctrl = readl(&adpll->clkctrl);
writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
/*
* ref_clk = 20/(n + 1);
* clkout_dco = ref_clk * m;
* clk_out = clkout_dco/m2;
*/
read_clkctrl = readl(&adpll->clkctrl) &
~(ADPLLJ_CLKCTRL_LPMODE |
ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
ADPLLJ_CLKCTRL_REGM4XEN);
writel(m2nval, &adpll->m2ndiv);
writel(mn2val, &adpll->mn2div);
/* Skip for modena(ADPLLS) */
if (adpllj) {
writel(sig_val, &adpll->fracdiv);
writel((read_clkctrl | hs_mod), &adpll->clkctrl);
}
/* Load M2, N2 dividers of ADPLL */
writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
/* Load M, N dividers of ADPLL */
writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
if (adpllj)
writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
&adpll->clkctrl);
/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
/* Wait for phase and freq lock */
while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
ADPLLJ_STATUS_PHSFRQLOCK)
;
}
static void unlock_pll_control_mmr(void)
{
/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
writel(0x1EDA4C3D, 0x481C5040);
writel(0x2FF1AC2B, 0x48140060);
writel(0xF757FDC0, 0x48140064);
writel(0xE2BC3A6D, 0x48140068);
writel(0x1EBF131D, 0x4814006c);
writel(0x6F361E05, 0x48140070);
}
static void mpu_pll_config(void)
{
pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
}
static void l3_pll_config(void)
{
u32 l3_osc_src, rd_osc_src = 0;
l3_osc_src = L3_OSC_SRC;
rd_osc_src = readl(OSC_SRC_CTRL);
if (OSC_SRC0 == l3_osc_src)
writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
else
writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
}
void ddr_pll_config(unsigned int ddrpll_m)
{
pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
}
void sata_pll_config(void)
{
/*
* This sequence for configuring the SATA PLL
* resident in the control module is documented
* in TI8148 TRM section 21.3.1
*/
writel(SATA_PLLCFG1, &spll->pllcfg1);
udelay(50);
writel(SATA_PLLCFG3, &spll->pllcfg3);
udelay(50);
writel(SATA_PLLCFG0_1, &spll->pllcfg0);
udelay(50);
writel(SATA_PLLCFG0_2, &spll->pllcfg0);
udelay(50);
writel(SATA_PLLCFG0_3, &spll->pllcfg0);
udelay(50);
writel(SATA_PLLCFG0_4, &spll->pllcfg0);
udelay(50);
while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
;
}
void enable_dmm_clocks(void)
{
writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
;
writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
;
while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
;
writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
;
writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
;
}
void setup_clocks_for_console(void)
{
unlock_pll_control_mmr();
/* UART0 */
writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
;
}
void setup_early_clocks(void)
{
setup_clocks_for_console();
}
/*
* Configure the PLL/PRCM for necessary peripherals
*/
void prcm_init(void)
{
/* Enable the control module */
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
/* Configure PLLs */
mpu_pll_config();
l3_pll_config();
sata_pll_config();
/* Enable the required peripherals */
enable_per_clocks();
}

20
arch/arm/mach-omap2/am33xx/emif4.c
View File

@ -28,26 +28,6 @@ static struct cm_device_inst *cm_device =
(struct cm_device_inst *)CM_DEVICE_INST;
#endif
#ifdef CONFIG_TI814X
void config_dmm(const struct dmm_lisa_map_regs *regs)
{
struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
enable_dmm_clocks();
writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
}
#endif
static void config_vtp(int nr)
{
writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,

2
arch/arm/mach-omap2/boot-common.c
View File

@ -183,7 +183,7 @@ void save_omap_boot_params(void)
gd->arch.omap_boot_mode = boot_mode;
#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
#if !defined(CONFIG_TI816X) && \
!defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
/* CH flags */

23
arch/arm/mach-tegra/Kconfig
View File

@ -177,6 +177,29 @@ source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
source "arch/arm/mach-tegra/tegra186/Kconfig"
config TEGRA_SPI
def_bool y
depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI
choice
prompt "UART to use for console"
depends on TEGRA_PINCTRL
default TEGRA_ENABLE_UARTA
config TEGRA_ENABLE_UARTA
bool "Use UARTA"
config TEGRA_ENABLE_UARTB
bool "Use UARTB"
config TEGRA_ENABLE_UARTC
bool "Use UARTC"
config TEGRA_ENABLE_UARTD
bool "Use UARTD"
endchoice
config TEGRA_GPU
bool "Enable setting up the GPU"
depends on TEGRA124 || TEGRA210

8
arch/arm/mach-tegra/tegra20/Kconfig
View File

@ -10,6 +10,12 @@ config TEGRA_PMU
config TEGRA_CLOCK_SCALING
bool
config TEGRA_UARTA_GPU
bool
config TEGRA_UARTA_SDIO1
bool
choice
prompt "Tegra20 board select"
optional
@ -43,6 +49,7 @@ config TARGET_TEC
config TARGET_TRIMSLICE
bool "Compulab TrimSlice board"
select BOARD_LATE_INIT
select TEGRA_UARTA_GPU
config TARGET_VENTANA
bool "NVIDIA Tegra20 Ventana evaluation board"
@ -51,6 +58,7 @@ config TARGET_VENTANA
config TARGET_COLIBRI_T20
bool "Toradex Colibri T20 board"
select BOARD_LATE_INIT
select TEGRA_UARTA_SDIO1
endchoice

8
arch/arm/mach-tegra/tegra30/Kconfig
View File

@ -1,5 +1,11 @@
if TEGRA30
config TEGRA_VDD_CORE_TPS62361B_SET3
bool
config TEGRA_VDD_CORE_TPS62366A_SET1
bool
choice
prompt "Tegra30 board select"
optional
@ -11,10 +17,12 @@ config TARGET_APALIS_T30
config TARGET_BEAVER
bool "NVIDIA Tegra30 Beaver evaluation board"
select BOARD_LATE_INIT
select TEGRA_VDD_CORE_TPS62366A_SET1
config TARGET_CARDHU
bool "NVIDIA Tegra30 Cardhu evaluation board"
select BOARD_LATE_INIT
select TEGRA_VDD_CORE_TPS62361B_SET3
config TARGET_COLIBRI_T30
bool "Toradex Colibri T30 board"

2
arch/m68k/config.mk
View File

@ -3,8 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
PLATFORM_CPPFLAGS += -D__M68K__
KBUILD_LDFLAGS += -n
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections

2
arch/microblaze/config.mk
View File

@ -6,8 +6,6 @@
# (C) Copyright 2004 Atmark Techno, Inc.
# Yasushi SHOJI <yashi@atmark-techno.com>
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections

2
arch/mips/config.mk
View File

@ -25,14 +25,12 @@ ifdef CONFIG_32BIT
PLATFORM_CPPFLAGS += -mabi=32
KBUILD_LDFLAGS += -m $(32bit-emul)
OBJCOPYFLAGS += -O $(32bit-bfd)
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000
endif
ifdef CONFIG_64BIT
PLATFORM_CPPFLAGS += -mabi=64
KBUILD_LDFLAGS += -m$(64bit-emul)
OBJCOPYFLAGS += -O $(64bit-bfd)
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000
endif
PLATFORM_CPPFLAGS += -D__MIPS__

2
arch/nios2/config.mk
View File

@ -4,8 +4,6 @@
# Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000
PLATFORM_CPPFLAGS += -D__NIOS2__
PLATFORM_CPPFLAGS += -G0

12
arch/powerpc/Kconfig
View File

@ -68,4 +68,16 @@ source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
source "arch/powerpc/lib/Kconfig"
config USE_UBOOTPATH
bool "Set a default 'uboot' value in the environment"
help
Many default environment scripts will check the "uboot" variable
to determine the name of the file to load via tftp that will then
be written to flash.
config UBOOTPATH
string "Value of the default 'uboot' value in the environment"
depends on USE_UBOOTPATH
default "u-boot.bin"
endmenu

1
arch/powerpc/config.mk
View File

@ -3,7 +3,6 @@
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
LDFLAGS_FINAL += --gc-sections
LDFLAGS_FINAL += --bss-plt
PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \

18
arch/powerpc/cpu/mpc83xx/cpu.c
View File

@ -180,24 +180,6 @@ void watchdog_reset (void)
}
#endif
#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_UEC_ETH)
uec_standard_init(bis);
#endif
#if defined(CONFIG_TSEC_ENET)
tsec_standard_init(bis);
#endif
return 0;
}
#endif /* !CONFIG_DM_ETH */
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()

38
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -1,6 +1,19 @@
menu "mpc85xx CPU"
depends on MPC85xx
config PPC_SPINTABLE_COMPATIBLE
depends on MP
def_bool y
help
To comply with ePAPR 1.1, the spin table has been moved to
cache-enabled memory. Old OS may not work with this change. A patch
is waiting to be accepted for Linux kernel. Other OS needs similar
fix to spin table. For OSes with old spin table code, we can enable
this temporary fix by setting environmental variable
"spin_table_compat". For new OSes, set "spin_table_compat=no". After
Linux is fixed, we can remove this macro and related code. For now,
it is enabled by default.
config SYS_CPU
default "mpc85xx"
@ -187,14 +200,6 @@ config TARGET_T1024RDB
imply CMD_EEPROM
imply PANIC_HANG
config TARGET_T1042RDB
bool "Support T1042RDB"
select ARCH_T1042
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select SYS_L3_SIZE_256KB
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
select ARCH_T1042
@ -204,15 +209,6 @@ config TARGET_T1042D4RDB
select SYS_L3_SIZE_256KB
imply PANIC_HANG
config TARGET_T1042RDB_PI
bool "Support T1042RDB_PI"
select ARCH_T1042
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select SYS_L3_SIZE_256KB
imply PANIC_HANG
config TARGET_T2080QDS
bool "Support T2080QDS"
select ARCH_T2080
@ -1297,6 +1293,9 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
config L2_CACHE
bool "Enable L2 cache support"
if HETROGENOUS_CLUSTERS
config SYS_MAPLE
@ -1324,6 +1323,11 @@ config SYS_ULB_CLK
config SYS_ETVPE_CLK
int
default 1
config MAX_DSP_CPUS
int
default 12 if ARCH_B4860
default 2 if ARCH_B4420
endif
config SYS_L2_SIZE_256KB

26
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -343,29 +343,3 @@ int fixup_cpu(void)
#endif
return 0;
}
#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_UEC_ETH)
uec_standard_init(bis);
#endif
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
tsec_standard_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif
#ifdef CONFIG_VSC9953
vsc9953_init(bis);
#endif
return 0;
}
#endif

8
arch/powerpc/cpu/mpc8xxx/srio.c
View File

@ -33,17 +33,17 @@
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
#endif
#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
#define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
#define CFG_SYS_MPC8xxx_GUTS_ADDR \
(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
#else
#error "No defines for DEVDISR_SRIO"
@ -230,7 +230,7 @@ host_ok:
void srio_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC8xxx_GUTS_ADDR;
int srio1_used = 0, srio2_used = 0;
u32 *devdisr;

14
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -8,12 +8,6 @@
/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
/*
* This macro should be removed when we no longer care about backwards
* compatibility with older operating systems.
*/
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548)
@ -23,7 +17,6 @@
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#elif defined(CONFIG_ARCH_P1021)
@ -93,11 +86,9 @@
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_T4240)
@ -136,8 +127,6 @@
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 2
@ -145,7 +134,6 @@
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CONFIG_MAX_DSP_CPUS 2
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 0
@ -173,7 +161,6 @@
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
@ -204,7 +191,6 @@
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000

2
arch/powerpc/include/asm/fsl_dma.h
View File

@ -117,7 +117,7 @@ typedef struct fsl_dma {
void dma_init(void);
int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
void dma_meminit(uint val, uint size);
void dma_meminit(uint size);
#endif
#endif

20
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -17,9 +17,7 @@
#if defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
defined(CONFIG_TARGET_T1042RDB) || \
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_ARCH_T1024)
#undef CFG_SYS_INIT_L3_ADDR
#define CFG_SYS_INIT_L3_ADDR 0xbff00000
@ -35,24 +33,6 @@
#define CFG_SYS_INIT_L3_ADDR 0xbff00000
#endif
#endif
#if defined(CONFIG_ARCH_P3041) || \
defined(CONFIG_ARCH_P4080) || \
defined(CONFIG_ARCH_P5040) || \
defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1
#endif
#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
/* The key used for verification of next level images
* is picked up from an Extension Table which has
* been verified by the ISBC (Internal Secure boot Code)
* in boot ROM of the SoC.
* The feature is only applicable in case of NOR boot and is
* not applicable in case of RAMBOOT (NAND, SD, SPI).
*/
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
#endif /* #ifdef CONFIG_NXP_ESBC */
#ifdef CONFIG_CHAIN_OF_TRUST

2
arch/riscv/config.mk
View File

@ -23,8 +23,6 @@ KBUILD_LDFLAGS += -m $(64bit-emul)
EFI_LDS := elf_riscv64_efi.lds
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
PLATFORM_CPPFLAGS += -ffixed-gp -fpic
PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \
-fdata-sections

10
arch/sandbox/include/asm/config.h
View File

@ -6,14 +6,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SANDBOX_ARCH
/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
#ifndef CONFIG_SANDBOX_SPI_MAX_BUS
#define CONFIG_SANDBOX_SPI_MAX_BUS 1
#endif
#ifndef CONFIG_SANDBOX_SPI_MAX_CS
#define CONFIG_SANDBOX_SPI_MAX_CS 10
#endif
#endif

1
arch/sh/config.mk
View File

@ -3,7 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
ifeq ($(CPU),sh2)
LDFLAGS_STANDALONE += -EB
endif

2
arch/x86/config.mk
View File

@ -3,8 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
PLATFORM_CPPFLAGS += -fomit-frame-pointer
PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \
$(call cc-option, -fno-unit-at-a-time))

1
arch/xtensa/include/asm/config.h
View File

@ -14,7 +14,6 @@
* restricting used physical memory to the first 128MB.
*/
#if XCHAL_HAVE_PTP_MMU
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (128 << 20)
#endif

2
board/Marvell/openrd/openrd.c
View File

@ -140,7 +140,7 @@ void mv_phy_init(char *name)
/* reset the phy */
miiphy_reset(name, devadr);
printf(PHY_NO" Initialized on %s\n", name);
printf("Initialized on %s\n", name);
}
void reset_phy(void)

27
board/cobra5272/README
View File

@ -77,21 +77,16 @@ in dir ./u-boot-x-x-x/
please first check:
in ./include/configs/cobra5272.h
in ./configs/cobra5272_defconfig
CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows:
#if 0
#define CONFIG_MONITOR_IS_IN_RAM
/* define if monitor is started from a pre-loader */
#endif
CONFIG_MONITOR_IS_IN_RAM has to be not present in the file
=> u-boot as single bootloader starting from flash
in board/cobra5272/config.mk CONFIG_TEXT_BASE should be
in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be
CONFIG_TEXT_BASE = 0xffe00000
CONFIG_TEXT_BASE=0xffe00000
=> linking address for u-boot as single bootloader stored in flash
@ -115,22 +110,18 @@ in dir ./u-boot-x-x-x/
host> make distclean
please modify the settings:
in ./configs/cobra5272_defconfig
in ./include/configs/cobra5272.h
CONFIG_MONITOR_IS_IN_RAM now has to be enabled, e. g. as follows:
CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows:
#if 1
#define CONFIG_MONITOR_IS_IN_RAM
/*define if monitor is started from a pre-loader */
#endif
CONFIG_MONITOR_IS_IN_RAM=y
=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
in board/cobra5272/config.mk CONFIG_TEXT_BASE should be
in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be
CONFIG_TEXT_BASE = 0x00020000
CONFIG_TEXT_BASE=0x00020000
=> target linking address for RAM

3
board/davinci/da8xxevm/Kconfig
View File

@ -37,6 +37,9 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "omapl138_lcdk"
config NAND_6BYTES_OOB_FREE_10BYTES_ECC
def_bool y
endif
source "board/ti/common/Kconfig"

2
board/freescale/common/fsl_chain_of_trust.c
View File

@ -143,7 +143,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
hdr_addr = (spl_image->entry_point + spl_image->size -
CONFIG_U_BOOT_HDR_SIZE);
FSL_U_BOOT_HDR_SIZE);
spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point);
/*
* In case of failure in validation, spl_validate_uboot would

18
board/freescale/common/fsl_validate.c
View File

@ -29,7 +29,7 @@
#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
((key_len) == 2 * KEY_SIZE_BYTES))
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
/* Global data structure */
static struct fsl_secboot_glb glb;
#endif
@ -63,7 +63,7 @@ self:
goto self;
}
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
static u32 check_ie(struct fsl_secboot_img_priv *img)
{
if (img->hdr.ie_flag & IE_FLAG_MASK)
@ -188,7 +188,7 @@ static u32 check_srk(struct fsl_secboot_img_priv *img)
{
#ifdef CONFIG_ESBC_HDR_LS
/* In LS, No SRK Flag as SRK is always present if IE not present*/
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
return !check_ie(img);
#endif
return 1;
@ -278,7 +278,7 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
}
#endif /* CONFIG_ESBC_HDR_LS */
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
static void install_ie_tbl(uintptr_t ie_tbl_addr,
struct fsl_secboot_img_priv *img)
@ -434,7 +434,7 @@ void fsl_secboot_handle_error(int error)
case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM:
case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN:
#endif
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
/*@fallthrough@*/
case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED:
case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY:
@ -571,7 +571,7 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
key_hash = 1;
}
#endif
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (!key_hash && check_ie(img))
key_hash = 1;
#endif
@ -705,7 +705,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
}
#endif
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (!key_found && check_ie(img)) {
ret = read_validate_ie_tbl(img);
if (ret != 0)
@ -851,7 +851,7 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
return -ENOMEM;
memset(img, 0, sizeof(struct fsl_secboot_img_priv));
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (glb.ie_addr)
img->ie_addr = glb.ie_addr;
#endif
@ -952,7 +952,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
else
ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES);
#if defined(CONFIG_FSL_ISBC_KEY_EXT)
#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT)
if (!hash_cmd && check_ie(img))
ret = 0;
#endif

4
board/freescale/t104xrdb/Kconfig
View File

@ -1,6 +1,4 @@
if TARGET_T1040RDB || TARGET_T1040D4RDB || \
TARGET_T1042RDB || TARGET_T1042D4RDB || \
TARGET_T1042RDB_PI
if TARGET_T1042D4RDB
config SYS_BOARD
default "t104xrdb"

2
board/freescale/t104xrdb/cpld.h
View File

@ -20,7 +20,7 @@ struct cpld_data {
u8 int_status; /* 0x12 - Interrupt status Register */
u8 flash_ctl_status; /* 0x13 - Flash control and status register */
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
#if defined(CONFIG_TARGET_T1042D4RDB)
u8 int_mask; /* 0x15 - Interrupt mask Register */
#else
u8 led_ctl_status; /* 0x15 - LED control and status register */

65
board/freescale/t104xrdb/eth.c
View File

@ -22,10 +22,6 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info memac_mdio_info;
unsigned int i;
int phy_addr = 0;
#ifdef CONFIG_VSC9953
phy_interface_t phy_int;
struct mii_dev *bus;
#endif
printf("Initializing Fman\n");
@ -43,25 +39,6 @@ int board_eth_init(struct bd_info *bis)
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
case PHY_INTERFACE_MODE_SGMII:
/* T1040RDB & T1040D4RDB only supports SGMII on
* DTSEC3
*/
fm_info_set_phy_address(FM1_DTSEC3,
CFG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_TARGET_T1042RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
fm_info_set_phy_address(i, 0);
/* T1042RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CFG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_TARGET_T1042D4RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
@ -107,48 +84,6 @@ int board_eth_init(struct bd_info *bis)
DEFAULT_FM_MDIO_NAME));
}
#ifdef CONFIG_VSC9953
/* SerDes configured for QSGMII */
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
for (i = 0; i < 4; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
vsc9953_port_enable(i);
}
}
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
for (i = 4; i < 8; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
vsc9953_port_enable(i);
}
}
/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
vsc9953_port_enable(8);
/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
CFG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
(0x80000000));
vsc9953_port_enable(9);
}
#endif
cpu_eth_init(bis);
#endif

19
board/freescale/t104xrdb/t104xrdb.c
View File

@ -34,7 +34,7 @@ int checkboard(void)
struct cpu_type *cpu = gd->arch.cpu;
u8 sw;
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
#if defined(CONFIG_TARGET_T1042D4RDB)
printf("Board: %sD4RDB\n", cpu->name);
#else
printf("Board: %sRDB\n", cpu->name);
@ -110,23 +110,6 @@ int misc_init_r(void)
CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
#if defined(CONFIG_TARGET_T1040D4RDB)
if (hwconfig("qe-tdm")) {
CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
MISC_MUX_QE_TDM);
printf("QECSR : 0x%02x, mux to qe-tdm\n",
CPLD_READ(sfp_ctl_status));
}
/* Mask all CPLD interrupt sources, except QSGMII interrupts */
if (CPLD_READ(sw_ver) < 0x03) {
debug("CPLD SW version 0x%02x doesn't support int_mask\n",
CPLD_READ(sw_ver));
} else {
CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
}
#endif
return 0;
}

4
board/google/Kconfig
View File

@ -6,6 +6,10 @@ if VENDOR_GOOGLE
config BIOSEMU
bool
select X86EMU_RAW_IO
config X86EMU_RAW_IO
bool
choice
prompt "Mainboard model"

14
board/samsung/common/gadget.c
View File

@ -7,14 +7,20 @@
#include <common.h>
#include <linux/usb/ch9.h>
#define EXYNOS_G_DNL_THOR_VENDOR_NUM 0x04E8
#define EXYNOS_G_DNL_THOR_PRODUCT_NUM 0x685D
#define EXYNOS_G_DNL_UMS_VENDOR_NUM 0x0525
#define EXYNOS_G_DNL_UMS_PRODUCT_NUM 0xA4A5
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
if (!strcmp(name, "usb_dnl_thor")) {
put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
put_unaligned(EXYNOS_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
put_unaligned(EXYNOS_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
} else if (!strcmp(name, "usb_dnl_ums")) {
put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor);
put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
put_unaligned(EXYNOS_G_DNL_UMS_VENDOR_NUM, &dev->idVendor);
put_unaligned(EXYNOS_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
} else {
put_unaligned(CONFIG_USB_GADGET_VENDOR_NUM, &dev->idVendor);
put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);

3
board/samsung/smdkv310/Kconfig
View File

@ -1,5 +1,8 @@
if TARGET_SMDKV310
config MIU_2BIT_INTERLEAVED
def_bool y
config SYS_BOARD
default "smdkv310"

2
board/siemens/common/board.c
View File

@ -93,7 +93,7 @@ int board_init(void)
gpmc_init();
#ifdef CONFIG_NAND_CS_INIT
#if CONFIG_IS_ENABLED(NAND_CS_INIT)
board_nand_cs_init();
#endif

2
board/siemens/draco/Kconfig
View File

@ -60,4 +60,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "etamin"
config NAND_CS_INIT
def_bool y
endif

9
board/siemens/draco/board.c
View File

@ -370,7 +370,14 @@ U_BOOT_CMD(
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
#ifdef CONFIG_NAND_CS_INIT
#if CONFIG_IS_ENABLED(NAND_CS_INIT)
#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800
#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00
#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00
#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807
#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e
#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80
/* GPMC definitions for second nand cs1 */
static const u32 gpmc_nand_config[] = {
ETAMIN_NAND_GPMC_CONFIG1,

4
board/sysam/stmark2/Kconfig
View File

@ -6,6 +6,10 @@ config CF_SBF
config EXTRA_CLOCK
def_bool y
config SERIAL_BOOT
def_bool y
depends on CF_SBF
config SYS_INPUT_CLKSRC
hex
default 30000000

7
board/timll/devkit8000/devkit8000.c
View File

@ -76,10 +76,11 @@ int board_init(void)
}
/* Configure GPMC registers for DM9000 */
#define DM9000_BASE 0x2c000000
static void gpmc_dm9000_config(void)
{
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
CONFIG_DM9000_BASE, GPMC_SIZE_16M);
DM9000_BASE, GPMC_SIZE_16M);
}
/*
@ -100,9 +101,7 @@ int misc_init_r(void)
#endif
#ifdef CONFIG_DRIVER_DM9000
/* Configure GPMC registers for DM9000 */
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
CONFIG_DM9000_BASE, GPMC_SIZE_16M);
gpmc_dm9000_config();
/* Use OMAP DIE_ID as MAC address */
if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {

4
cmd/Kconfig
View File

@ -526,6 +526,10 @@ config CMD_THOR_DOWNLOAD
There is no documentation about this within the U-Boot source code
but you should be able to find something on the interwebs.
config THOR_RESET_OFF
bool "thor: Disable reset on completion"
depends on CMD_THOR_DOWNLOAD
config CMD_ZBOOT
bool "zboot - x86 boot command"
help

15
cmd/i2c.c
View File

@ -98,7 +98,7 @@ static uint i2c_mm_last_alen;
* pairs. The following macros take care of this */
#if defined(CFG_SYS_I2C_NOPROBES)
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
static struct
{
uchar bus;
@ -1764,8 +1764,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \
CONFIG_IS_ENABLED(DM_I2C)
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@ -1915,10 +1914,9 @@ static struct cmd_tbl cmd_i2c_sub[] = {
U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
#endif
U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \
defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif /* CONFIG_I2C_MULTI_BUS */
#endif
#if defined(CONFIG_I2C_EDID)
U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
#endif /* CONFIG_I2C_EDID */
@ -1992,10 +1990,9 @@ static char i2c_help_text[] =
"i2c " /* That's the prefix for the crc32 command below. */
#endif
"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \
defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C)
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C)
"i2c dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
#endif
#if defined(CONFIG_I2C_EDID)
"i2c edid chip - print EDID configuration information\n"
#endif /* CONFIG_I2C_EDID */

2
common/spl/Kconfig
View File

@ -1347,7 +1347,7 @@ config SPL_USB_HOST
config SPL_USB_STORAGE
bool "Support loading from USB"
depends on SPL_USB_HOST && !(BLK && !DM_USB)
depends on SPL_USB_HOST
help
Enable support for USB devices in SPL. This allows use of USB
devices such as hard drives and flash drivers for loading U-Boot.

1
configs/10m50_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_NIOS2=y
CONFIG_SYS_CONFIG_NAME="10m50_devboard"
CONFIG_MONITOR_IS_IN_RAM=y
CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1

2
configs/3c120_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_NIOS2=y
CONFIG_SYS_CONFIG_NAME="3c120_devboard"
CONFIG_MONITOR_IS_IN_RAM=y
CONFIG_SYS_MALLOC_LEN=0x20000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
@ -39,6 +40,7 @@ CONFIG_MISC=y
CONFIG_ALTERA_SYSID=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_CFI_FLASH=y
CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y

11
configs/M5208EVBE_defconfig
View File

@ -26,8 +26,18 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5208EVBe"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -37,6 +47,7 @@ CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=254

11
configs/M5235EVB_Flash32_defconfig
View File

@ -34,7 +34,17 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="u-boot.bin"
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5235EVB"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -44,6 +54,7 @@ CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

11
configs/M5235EVB_defconfig
View File

@ -34,7 +34,17 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="u-boot.bin"
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5235EVB"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -44,6 +54,7 @@ CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

1
configs/M5249EVB_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_FLASH_CHECKSUM=y

4
configs/M5253DEMO_defconfig
View File

@ -25,7 +25,10 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_OVERWRITE_ETHADDR_ONCE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5253DEMO"
# CONFIG_BLOCK_CACHE is not set
CONFIG_SYS_IDE_MAXBUS=1
CONFIG_SYS_ATA_STRIDE=4
@ -44,4 +47,5 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_MAX_FLASH_SECT=2048
CONFIG_USE_SYS_MAX_FLASH_BANKS=y
CONFIG_DRIVER_DM9000=y
CONFIG_DM9000_BYTE_SWAPPED=y
CONFIG_MCFUART=y

11
configs/M5272C3_defconfig
View File

@ -27,7 +27,17 @@ CONFIG_MII_INIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5272C3"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFE00201
@ -56,6 +66,7 @@ CONFIG_SYS_OR7_PRELIM=0xFFC0007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

2
configs/M5275EVB_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_CMD_MII=y
CONFIG_MII_INIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_OVERWRITE_ETHADDR_ONCE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
@ -41,6 +42,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=11
CONFIG_MCFFEC=y

11
configs/M5282EVB_defconfig
View File

@ -27,11 +27,22 @@ CONFIG_MII_INIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5282EVB"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_FLASH_CHECKSUM=y

12
configs/M53017EVB_defconfig
View File

@ -28,8 +28,18 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M53017"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -39,7 +49,9 @@ CONFIG_SYS_I2C_SPEED=80000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_SPANSION_S29WS_N=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

11
configs/M5329AFEE_defconfig
View File

@ -27,8 +27,18 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5329EVB"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -39,6 +49,7 @@ CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

11
configs/M5329BFEE_defconfig
View File

@ -28,8 +28,18 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5329EVB"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -40,6 +50,7 @@ CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

11
configs/M5373EVB_defconfig
View File

@ -28,8 +28,18 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="M5373EVB"
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_UDP_CHECKSUM=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.162.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.162.1.2"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.162.1.1"
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
@ -40,6 +50,7 @@ CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=137

7
configs/MCR3000_defconfig
View File

@ -55,6 +55,12 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.0.3"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.0.0.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.0.1"
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0x4000801
CONFIG_SYS_OR0_PRELIM=0xFFC00926
@ -83,6 +89,7 @@ CONFIG_SYS_OR7_PRELIM=0xFFFF810A
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=35
CONFIG_MTD_RAW_NAND=y

7
configs/MPC837XERDB_defconfig
View File

@ -148,6 +148,7 @@ CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y
CONFIG_FSL_SERDES=y
CONFIG_USE_UBOOTPATH=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -178,6 +179,10 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="TSEC0"
CONFIG_USE_HOSTNAME=y
CONFIG_HOSTNAME="mpc837x_rdb"
CONFIG_USE_ROOTPATH=y
CONFIG_ROOTPATH="/nfsroot"
CONFIG_FSL_SATA=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_SYS_BR0_PRELIM_BOOL=y
@ -195,8 +200,10 @@ CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=400000
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC_PIN_MUX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_EMPTY_INFO=y
CONFIG_SYS_FLASH_PROTECTION=y

15
configs/MPC8548CDS_36BIT_defconfig
View File

@ -13,7 +13,10 @@ CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
CONFIG_PCIE1=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_MONITOR_LEN=524288
@ -45,6 +48,17 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC0"
CONFIG_USE_HOSTNAME=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.168.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.253"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_ROOTPATH=y
CONFIG_ROOTPATH="/nfsroot"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y
@ -68,6 +82,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_EMPTY_INFO=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=128

15
configs/MPC8548CDS_defconfig
View File

@ -13,7 +13,10 @@ CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
CONFIG_PCIE1=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
@ -44,6 +47,17 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC0"
CONFIG_USE_HOSTNAME=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.168.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.253"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_ROOTPATH=y
CONFIG_ROOTPATH="/nfsroot"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y
@ -67,6 +81,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_EMPTY_INFO=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=128

15
configs/MPC8548CDS_legacy_defconfig
View File

@ -13,8 +13,11 @@ CONFIG_SRIO1=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_TARGET_MPC8548CDS_LEGACY=y
CONFIG_USE_UBOOTPATH=y
CONFIG_UBOOTPATH="8548cds/u-boot.bin"
CONFIG_PCIE1=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
@ -44,6 +47,17 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="8548cds/uImage.uboot"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC0"
CONFIG_USE_HOSTNAME=y
CONFIG_USE_GATEWAYIP=y
CONFIG_GATEWAYIP="192.168.1.1"
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.253"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_ROOTPATH=y
CONFIG_ROOTPATH="/nfsroot"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
CONFIG_SPD_EEPROM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y
@ -67,6 +81,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_FLASH_EMPTY_INFO=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_SECT=128

3
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -16,9 +16,11 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
@ -81,6 +83,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_36BIT_NOR_defconfig
View File

@ -9,8 +9,10 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
@ -49,6 +51,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -14,9 +14,11 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
@ -71,6 +73,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -16,9 +16,11 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
@ -73,6 +75,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_NAND_defconfig
View File

@ -16,9 +16,11 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_SYS_MONITOR_LEN=786432
@ -80,6 +82,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_NOR_defconfig
View File

@ -9,8 +9,10 @@ CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_SYS_MONITOR_LEN=786432
@ -48,6 +50,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -14,9 +14,11 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_SYS_MONITOR_LEN=786432
@ -70,6 +72,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -16,9 +16,11 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_SYS_MONITOR_LEN=786432
@ -72,6 +74,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

3
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -16,9 +16,11 @@ CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_L2_CACHE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_USE_UBOOTPATH=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
@ -82,6 +84,7 @@ CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eTSEC1"
CONFIG_USE_ROOTPATH=y
CONFIG_FSL_SATA_V2=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y

Some files were not shown because too many files have changed in this diff Show More