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arm: dts: socfpga: stratix10: Add freeze controller node
The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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@ -2,7 +2,7 @@
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/*
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/*
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* U-Boot additions
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* U-Boot additions
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*
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*
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* Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
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* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
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*/
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*/
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#include "socfpga_stratix10-u-boot.dtsi"
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#include "socfpga_stratix10-u-boot.dtsi"
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/{
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/{
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aliases {
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aliases {
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spi0 = &qspi;
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spi0 = &qspi;
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freeze_br0 = &freeze_controller;
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};
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soc {
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freeze_controller: freeze_controller@f9000450 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0xf9000450 0x00000010>;
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status = "disabled";
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};
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};
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};
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};
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};
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