arm: dts: socfpga: stratix10: Add freeze controller node

The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Dinesh Maniyam 2022-05-31 16:15:17 +08:00 committed by Tien Fong Chee
parent 7f85330782
commit 5474fb894c

View File

@ -2,7 +2,7 @@
/* /*
* U-Boot additions * U-Boot additions
* *
* Copyright (C) 2019-2020 Intel Corporation <www.intel.com> * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/ */
#include "socfpga_stratix10-u-boot.dtsi" #include "socfpga_stratix10-u-boot.dtsi"
@ -10,6 +10,15 @@
/{ /{
aliases { aliases {
spi0 = &qspi; spi0 = &qspi;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@f9000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0xf9000450 0x00000010>;
status = "disabled";
};
}; };
}; };