mirror of
				https://github.com/smaeul/u-boot.git
				synced 2025-11-04 05:50:17 +00:00 
			
		
		
		
	ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
Sets DDR configuration parameter cdr1 before all other settings to support case 0.9v VDD is enabled for some SoCs Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
		
							parent
							
								
									23a12cb3d0
								
							
						
					
					
						commit
						554d33f3db
					
				@ -95,6 +95,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 | 
			
		||||
	if (step == 2)
 | 
			
		||||
		goto step2;
 | 
			
		||||
 | 
			
		||||
	/* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
 | 
			
		||||
	ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 | 
			
		||||
 | 
			
		||||
	if (regs->ddr_eor)
 | 
			
		||||
		ddr_out32(&ddr->eor, regs->ddr_eor);
 | 
			
		||||
 | 
			
		||||
@ -183,7 +186,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 | 
			
		||||
	ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 | 
			
		||||
	ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 | 
			
		||||
	ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 | 
			
		||||
	ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 | 
			
		||||
#ifdef CONFIG_DEEP_SLEEP
 | 
			
		||||
	if (is_warm_boot()) {
 | 
			
		||||
		ddr_out32(&ddr->sdram_cfg_2,
 | 
			
		||||
 | 
			
		||||
		Loading…
	
	
			
			x
			
			
		
	
		Reference in New Issue
	
	Block a user