Merge tag 'qcom-fixes-2025.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon

CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/24841

The clk_stub, regulator, and pinctrl fixes enable the sdcard on the RB5
dev board (and sm8250 devices broadly). clk_stub is only enabled in
qcom_defconfig and the others are qcom specific so these shouldn't
affect other platforms.

Lastly, a small ufetch fix from Sam which gets color rendering correctly
on U-Boots framebuffer video device.

cmd/ufetch.c

@@ -24,8 +24,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define LINE_WIDTH 40
-#define BLUE "\033[38;5;4m"
+#define BLUE "\033[34m"
-#define YELLOW "\033[38;5;11m"
+#define YELLOW "\033[33m"
 #define BOLD "\033[1m"
 #define RESET "\033[0m"
 static const char * const logo_lines[] = {

configs/qcom_defconfig

@@ -58,6 +58,7 @@ CONFIG_CLK_QCOM_SM8550=y
 CONFIG_CLK_QCOM_SM8650=y
 CONFIG_CLK_QCOM_SC7280=y
 CONFIG_CLK_QCOM_X1E80100=y
+CONFIG_CLK_STUB=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_SCSI=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000

drivers/clk/Kconfig

@@ -96,6 +96,13 @@ config SPL_CLK_GPIO
 	  Enable this option to add GPIO-controlled clock gate driver
 	  in U-Boot SPL.
 
+config CLK_STUB
+	bool "Stub clock driver"
+	depends on CLK
+	help
+	  Enable this to provide a stub clock driver for non-essential clock
+	  controllers.
+
 config CLK_BCM6345
 	bool "Clock controller driver for BCM6345"
 	depends on CLK && ARCH_BMIPS

drivers/clk/Makefile

@@ -11,6 +11,7 @@ obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
 obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-fixed-factor.o
 obj-$(CONFIG_$(PHASE_)CLK_COMPOSITE_CCF) += clk-composite.o
 obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o
+obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o
 
 obj-y += adi/
 obj-y += analogbits/

drivers/clk/clk-stub.c

@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Stub clk driver for non-essential clocks.
+ *
+ * This driver should be used for clock controllers
+ * which are described as dependencies in DT but aren't
+ * actually necessary for hardware functionality.
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+
+/* NOP parent nodes to stub clocks */
+static const struct udevice_id nop_parent_ids[] = {
+	{ .compatible = "qcom,rpm-proc" },
+	{ .compatible = "qcom,glink-rpm" },
+	{ .compatible = "qcom,rpm-sm6115" },
+	{ }
+};
+
+U_BOOT_DRIVER(nop_parent) = {
+	.name = "nop_parent",
+	.id = UCLASS_NOP,
+	.of_match = nop_parent_ids,
+	.bind = dm_scan_fdt_dev,
+	.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
+static ulong stub_clk_set_rate(struct clk *clk, ulong rate)
+{
+	return (clk->rate = rate);
+}
+
+static ulong stub_clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static int stub_clk_nop(struct clk *clk)
+{
+	return 0;
+}
+
+static struct clk_ops stub_clk_ops = {
+	.set_rate = stub_clk_set_rate,
+	.get_rate = stub_clk_get_rate,
+	.enable = stub_clk_nop,
+	.disable = stub_clk_nop,
+};
+
+static const struct udevice_id stub_clk_ids[] = {
+	{ .compatible = "qcom,rpmcc" },
+	{ .compatible = "qcom,sm8150-rpmh-clk" },
+	{ .compatible = "qcom,sm8250-rpmh-clk" },
+	{ .compatible = "qcom,sm8550-rpmh-clk" },
+	{ .compatible = "qcom,sm8650-rpmh-clk" },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_stub) = {
+	.name = "clk_stub",
+	.id = UCLASS_CLK,
+	.ops = &stub_clk_ops,
+	.of_match = stub_clk_ids,
+	.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+

drivers/pinctrl/qcom/pinctrl-sm8250.c

@@ -107,7 +107,7 @@ static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, uns
 static struct msm_pinctrl_data sm8250_data = {
 	.pin_data = {
 		.pin_offsets = sm8250_pin_offsets,
-		.pin_count = ARRAY_SIZE(sm8250_pin_offsets),
+		.pin_count = 184,
 		.special_pins_start = 180,
 		.special_pins_data = sm8250_special_pins_data,
 	},

drivers/power/regulator/qcom-rpmh-regulator.c

@@ -481,6 +481,13 @@ static const struct rpmh_vreg_init_data pm8150_vreg_data[] = {
 
 static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = {
 	RPMH_VREG("ldo1",   "ldo%s1",  &pmic5_pldo_lv,   "vdd-l1-l8"),
+	RPMH_VREG("ldo4",   "ldo%s4",  &pmic5_pldo,      "vdd-l4-l5-l6"),
+	RPMH_VREG("ldo5",   "ldo%s5",  &pmic5_pldo,      "vdd-l4-l5-l6"),
+	RPMH_VREG("ldo6",   "ldo%s6",  &pmic5_pldo,      "vdd-l4-l5-l6"),
+	RPMH_VREG("ldo7",   "ldo%s7",  &pmic5_pldo,      "vdd-l7-l11"),
+	RPMH_VREG("ldo8",   "ldo%s8",  &pmic5_pldo_lv,   "vdd-l1-l8"),
+	RPMH_VREG("ldo9",   "ldo%s9",  &pmic5_pldo,      "vdd-l9-l10"),
+	RPMH_VREG("ldo10",  "ldo%s10", &pmic5_pldo,      "vdd-l9-l10"),
 	RPMH_VREG("ldo11",  "ldo%s11", &pmic5_pldo,      "vdd-l7-l11"),
 	{}
 };