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arm: Migrate GICV2 / GICV3 to Kconfig

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Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig.  We still have the GIC
related registers that need to be handled more cleanly but start by
moving this symbol to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-08-19 14:19:39 -04:00
parent 4d540a3a81
commit 5afdcca019
18 changed files with 36 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/Kconfig
View File

@ -63,6 +63,12 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
endif endif
endif endif
config GICV2
bool
config GICV3
bool
config GIC_V3_ITS config GIC_V3_ITS
bool "ARM GICV3 ITS" bool "ARM GICV3 ITS"
select REGMAP select REGMAP
@ -953,6 +959,7 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM select DM
select DM_SERIAL select DM_SERIAL
select GICV2
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL select OF_CONTROL
@ -1063,6 +1070,7 @@ config ARCH_VERSAL
select DM_ETH if NET select DM_ETH if NET
select DM_MMC if MMC select DM_MMC if MMC
select DM_SERIAL select DM_SERIAL
select GICV3
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select OF_CONTROL select OF_CONTROL
select SOC_DEVICE select SOC_DEVICE
@ -1132,6 +1140,7 @@ config ARCH_ZYNQMP
select DM_SPI if SPI select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI select DM_SPI_FLASH if DM_SPI
select FIRMWARE select FIRMWARE
select GICV2
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select OF_CONTROL select OF_CONTROL
select SPL_BOARD_INIT if SPL select SPL_BOARD_INIT if SPL
@ -1881,6 +1890,7 @@ config TARGET_DURIAN
config TARGET_PRESIDIO_ASIC config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform" bool "Support Cortina Presidio ASIC Platform"
select ARM64 select ARM64
select GICV2
config TARGET_XENGUEST_ARM64 config TARGET_XENGUEST_ARM64
bool "Xen guest ARM64" bool "Xen guest ARM64"

8
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
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@ -4,6 +4,7 @@ config ARCH_LS1012A
select ARM_ERRATA_855873 if !TFABOOT select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH2 select FSL_LSCH2
select GICV2
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
select SYS_FSL_DDR_BE select SYS_FSL_DDR_BE
@ -25,6 +26,7 @@ config ARCH_LS1028A
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH3 select FSL_LSCH3
select GICV3
select NXP_LSCH3_2 select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
@ -58,6 +60,7 @@ config ARCH_LS1043A
select ARM_ERRATA_855873 if !TFABOOT select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH2 select FSL_LSCH2
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
@ -91,6 +94,7 @@ config ARCH_LS1046A
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH2 select FSL_LSCH2
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
@ -129,6 +133,7 @@ config ARCH_LS1088A
select ARM_ERRATA_855873 if !TFABOOT select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH3 select FSL_LSCH3
select GICV3
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
select SYS_FSL_DDR select SYS_FSL_DDR
@ -175,6 +180,7 @@ config ARCH_LS2080A
select ARM_ERRATA_833471 select ARM_ERRATA_833471
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH3 select FSL_LSCH3
select GICV3
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
select SYS_FSL_DDR select SYS_FSL_DDR
@ -223,6 +229,7 @@ config ARCH_LX2162A
bool bool
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select FSL_LSCH3 select FSL_LSCH3
select GICV3
select NXP_LSCH3_2 select NXP_LSCH3_2
select SYS_HAS_SERDES select SYS_HAS_SERDES
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
@ -255,6 +262,7 @@ config ARCH_LX2160A
bool bool
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select FSL_LSCH3 select FSL_LSCH3
select GICV3
select HAS_FSL_XHCI_USB if USB_HOST select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2 select NXP_LSCH3_2
select SYS_HAS_SERDES select SYS_HAS_SERDES

2
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -123,7 +123,6 @@
#elif defined(CONFIG_ARCH_LS1088A) #elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_GICV3
#define CONFIG_SYS_PAGE_SIZE 0x10000 #define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4 #define SRDS_MAX_LANES 4
@ -235,7 +234,6 @@
#elif defined(CONFIG_ARCH_LS1028A) #elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400 #define CONFIG_FSL_TZASC_400

12
arch/arm/mach-rmobile/Kconfig.64
View File

@ -4,61 +4,73 @@ menu "Select Target SoC"
config R8A774A1 config R8A774A1
bool "Renesas SoC R8A774A1" bool "Renesas SoC R8A774A1"
select GICV2
imply CLK_R8A774A1 imply CLK_R8A774A1
imply PINCTRL_PFC_R8A774A1 imply PINCTRL_PFC_R8A774A1
config R8A774B1 config R8A774B1
bool "Renesas SoC R8A774B1" bool "Renesas SoC R8A774B1"
select GICV2
imply CLK_R8A774B1 imply CLK_R8A774B1
imply PINCTRL_PFC_R8A774B1 imply PINCTRL_PFC_R8A774B1
config R8A774C0 config R8A774C0
bool "Renesas SoC R8A774C0" bool "Renesas SoC R8A774C0"
select GICV2
imply CLK_R8A774C0 imply CLK_R8A774C0
imply PINCTRL_PFC_R8A774C0 imply PINCTRL_PFC_R8A774C0
config R8A774E1 config R8A774E1
bool "Renesas SoC R8A774E1" bool "Renesas SoC R8A774E1"
select GICV2
imply CLK_R8A774E1 imply CLK_R8A774E1
imply PINCTRL_PFC_R8A774E1 imply PINCTRL_PFC_R8A774E1
config R8A7795 config R8A7795
bool "Renesas SoC R8A7795" bool "Renesas SoC R8A7795"
select GICV2
imply CLK_R8A7795 imply CLK_R8A7795
imply PINCTRL_PFC_R8A7795 imply PINCTRL_PFC_R8A7795
config R8A7796 config R8A7796
bool "Renesas SoC R8A7796" bool "Renesas SoC R8A7796"
select GICV2
imply CLK_R8A7796 imply CLK_R8A7796
imply PINCTRL_PFC_R8A7796 imply PINCTRL_PFC_R8A7796
config R8A77965 config R8A77965
bool "Renesas SoC R8A77965" bool "Renesas SoC R8A77965"
select GICV2
imply CLK_R8A77965 imply CLK_R8A77965
imply PINCTRL_PFC_R8A77965 imply PINCTRL_PFC_R8A77965
config R8A77970 config R8A77970
bool "Renesas SoC R8A77970" bool "Renesas SoC R8A77970"
select GICV2
imply CLK_R8A77970 imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970 imply PINCTRL_PFC_R8A77970
config R8A77980 config R8A77980
bool "Renesas SoC R8A77980" bool "Renesas SoC R8A77980"
select GICV2
imply CLK_R8A77980 imply CLK_R8A77980
imply PINCTRL_PFC_R8A77980 imply PINCTRL_PFC_R8A77980
config R8A77990 config R8A77990
bool "Renesas SoC R8A77990" bool "Renesas SoC R8A77990"
select GICV2
imply CLK_R8A77990 imply CLK_R8A77990
imply PINCTRL_PFC_R8A77990 imply PINCTRL_PFC_R8A77990
config R8A77995 config R8A77995
bool "Renesas SoC R8A77995" bool "Renesas SoC R8A77995"
select GICV2
imply CLK_R8A77995 imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995 imply PINCTRL_PFC_R8A77995
config R8A779A0 config R8A779A0
bool "Renesas SoC R8A779A0" bool "Renesas SoC R8A779A0"
select GICV3
imply CLK_R8A779A0 imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0 imply PINCTRL_PFC_R8A779A0

2
arch/arm/mach-tegra/Kconfig
View File

@ -124,6 +124,7 @@ config TEGRA124
config TEGRA210 config TEGRA210
bool "Tegra210 family" bool "Tegra210 family"
select GICV2
select TEGRA_ARMV8_COMMON select TEGRA_ARMV8_COMMON
select TEGRA_CLKRST select TEGRA_CLKRST
select TEGRA_GPIO select TEGRA_GPIO
@ -137,6 +138,7 @@ config TEGRA210
config TEGRA186 config TEGRA186
bool "Tegra186 family" bool "Tegra186 family"
select DM_MAILBOX select DM_MAILBOX
select GICV2
select TEGRA186_BPMP select TEGRA186_BPMP
select TEGRA186_CLOCK select TEGRA186_CLOCK
select TEGRA186_GPIO select TEGRA186_GPIO

3
arch/arm/mach-versal/Kconfig
View File

@ -21,9 +21,6 @@ config SYS_CONFIG_NAME
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration. will be used for board configuration.
config GICV3
def_bool y
config SYS_MALLOC_LEN config SYS_MALLOC_LEN
default 0x2000000 default 0x2000000

9
include/configs/falcon.h
View File

@ -11,14 +11,13 @@
#include "rcar-gen3-common.h" #include "rcar-gen3-common.h"
/* Generic Interrupt Controller Definitions */ /*
#ifdef CONFIG_GICV2 * Generic Interrupt Controller Definitions. Undefine v2 locations and define
#undef CONFIG_GICV2 * v3 locations.
*/
#undef GICD_BASE #undef GICD_BASE
#undef GICC_BASE #undef GICC_BASE
#undef GICR_BASE #undef GICR_BASE
#endif
#define CONFIG_GICV3
#define GICD_BASE 0xF1000000 #define GICD_BASE 0xF1000000
#define GICR_BASE 0xF1060000 #define GICR_BASE 0xF1060000

2
include/configs/ls1012a_common.h
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@ -6,8 +6,6 @@
#ifndef __LS1012A_COMMON_H #ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H #define __LS1012A_COMMON_H
#define CONFIG_GICV2
#include <asm/arch/config.h> #include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h> #include <linux/sizes.h>

1
include/configs/ls1043a_common.h
View File

@ -27,7 +27,6 @@
#endif #endif
#define CONFIG_REMAKE_ELF #define CONFIG_REMAKE_ELF
#define CONFIG_GICV2
#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h> #include <asm/arch/config.h>

1
include/configs/ls1046a_common.h
View File

@ -27,7 +27,6 @@
#endif #endif
#define CONFIG_REMAKE_ELF #define CONFIG_REMAKE_ELF
#define CONFIG_GICV2
#include <asm/arch/config.h> #include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/stream_id_lsch2.h>

1
include/configs/ls2080a_common.h
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@ -8,7 +8,6 @@
#define __LS2_COMMON_H #define __LS2_COMMON_H
#define CONFIG_REMAKE_ELF #define CONFIG_REMAKE_ELF
#define CONFIG_GICV3
#include <asm/arch/stream_id_lsch3.h> #include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h> #include <asm/arch/config.h>

1
include/configs/lx2160a_common.h
View File

@ -12,7 +12,6 @@
#define CONFIG_REMAKE_ELF #define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_MEMAC #define CONFIG_FSL_MEMAC

1
include/configs/presidio_asic.h
View File

@ -23,7 +23,6 @@
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
* does not yet support DT. Thus define it here. * does not yet support DT. Thus define it here.
*/ */
#define CONFIG_GICV2
#define GICD_BASE 0xf7011000 #define GICD_BASE 0xf7011000
#define GICC_BASE 0xf7012000 #define GICC_BASE 0xf7012000

1
include/configs/rcar-gen3-common.h
View File

@ -26,7 +26,6 @@
#define CONFIG_INITRD_TAG #define CONFIG_INITRD_TAG
/* Generic Interrupt Controller Definitions */ /* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF1010000 #define GICD_BASE 0xF1010000
#define GICC_BASE 0xF1020000 #define GICC_BASE 0xF1020000

5
include/configs/socfpga_soc64_common.h
View File

@ -115,11 +115,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"then source ${scriptaddr}; fi\0" \ "then source ${scriptaddr}; fi\0" \
"socfpga_legacy_reset_compat=1\0" "socfpga_legacy_reset_compat=1\0"
/*
* Generic Interrupt Controller Definitions
*/
#define CONFIG_GICV2
/* /*
* External memory configurations * External memory configurations
*/ */

3
include/configs/tegra186-common.h
View File

@ -17,9 +17,6 @@
* Physical Memory Map * Physical Memory Map
*/ */
/* Generic Interrupt Controller */
#define CONFIG_GICV2
#undef FDTFILE #undef FDTFILE
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ #define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \

3
include/configs/tegra210-common.h
View File

@ -14,9 +14,6 @@
*/ */
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
/* Generic Interrupt Controller */
#define CONFIG_GICV2
/* /*
* Memory layout for where various images get loaded by boot scripts: * Memory layout for where various images get loaded by boot scripts:
* *

1
include/configs/xilinx_zynqmp.h
View File

@ -15,7 +15,6 @@
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */ /* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF9010000 #define GICD_BASE 0xF9010000
#define GICC_BASE 0xF9020000 #define GICC_BASE 0xF9020000