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arm64: xilinx: Put ethernet phys to mdio node

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All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-09-22 12:35:36 +02:00
parent 2036621a61
commit 5c214bac46
11 changed files with 85 additions and 41 deletions
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10
arch/arm/dts/zynqmp-dlc21-revA.dts
View File

@ -88,9 +88,13 @@
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

10
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
View File

@ -81,10 +81,14 @@
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
phy0: ethernet-phy@0 { /* marwell m88e1512 */
reg = <0>;
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { /* marwell m88e1512 */
reg = <0>;
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
};
};

10
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View File

@ -110,10 +110,14 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
};
};

10
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
View File

@ -106,9 +106,13 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii";
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
};
};
};

10
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
View File

@ -106,9 +106,13 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii";
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
};
};
};

10
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
View File

@ -91,9 +91,13 @@
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

8
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -97,8 +97,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

16
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -90,12 +90,16 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};

8
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
View File

@ -88,8 +88,12 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};
};

26
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View File

@ -116,17 +116,21 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
};
};
};

8
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
View File

@ -77,8 +77,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};