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riscv: Weakly define invalidate_icache_range()

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Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Series-to: Rick Chen <rick@andestech.com>
Series-to: Leo <ycliang@andestech.com>
Series-cc: u-boot@lists.denx.de

Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2023-02-04 14:03:10 -06:00
parent cbba1b7766
commit 5e81022e53
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/lib/cache.c
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@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end)
{ {
} }
void invalidate_icache_range(unsigned long start, unsigned long end) __weak void invalidate_icache_range(unsigned long start, unsigned long end)
{ {
/* /*
* RISC-V does not have an instruction for invalidating parts of the * RISC-V does not have an instruction for invalidating parts of the