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sunxi-nand: fix the PIO instead of DMA implementation

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The sunxi nand SPL loader was broken at least for SUN4I,
SUN5I and SUN7I SOCs since the implementation change
from DMA to PIO usage - commit 6ddbb1e.

Root cause for this issue is the NFC control flag NFC_CTL_RAM_METHOD
being set by method nand_apply_config.

This flag controls the bus being used for the NFCs internal RAM access.
It must be set for the DMA use case only.
See A33_Nand_Flash_Controller_Specification.pdf page 12.

This fix is tested by myself on a Cubietruck A20 board.
Others should test it on new generation SOCs as well.

Signed-off-by: Markus Hoffrogge <mhoffrogge@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Markus Hoffrogge 2022-06-30 01:26:39 +02:00 committed by Andre Przywara
parent 4a9f37df1d
commit 5fd30ed785
1 changed files with 1 additions and 1 deletions
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2
drivers/mtd/nand/raw/sunxi_nand_spl.c
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@ -208,7 +208,7 @@ static void nand_apply_config(const struct nfc_config *conf)
val = readl(SUNXI_NFC_BASE + NFC_CTL);
val &= ~NFC_CTL_PAGE_SIZE_MASK;
writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
writel(val | NFC_CTL_PAGE_SIZE(conf->page_size),
SUNXI_NFC_BASE + NFC_CTL);
writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);