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andes: cpu: Enable cache and TLB ECC support

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Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
This commit is contained in:
Leo Yu-Chi Liang 2023-12-26 14:17:35 +08:00
parent bf12bb99d8
commit 61d5c543f3
2 changed files with 5 additions and 1 deletions
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3
arch/riscv/cpu/andesv5/cpu.c
View File

@ -35,7 +35,8 @@ void harts_early_init(void)
mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl_val |= MCACHE_CTL_IC_EN;

3
arch/riscv/include/asm/arch-andes/csr.h
View File

@ -18,11 +18,14 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_IC_ECCEN BIT(3)
#define MCACHE_CTL_DC_ECCEN BIT(5)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_TLB_ECCEN BIT(18)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)