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drivers: pinctrl: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-07-20 14:40:48 +02:00 committed by Tom Rini
parent c94a0359c9
commit 62b66c39c2
14 changed files with 0 additions and 15 deletions
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1
drivers/pinctrl/exynos/pinctrl-exynos.h
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@ -92,7 +92,6 @@ struct exynos_pinctrl_config_data {
const unsigned int value; const unsigned int value;
}; };
void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf, void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
unsigned int num_conf, unsigned long base); unsigned int num_conf, unsigned long base);
int exynos_pinctrl_set_state(struct udevice *dev, int exynos_pinctrl_set_state(struct udevice *dev,

1
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
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@ -729,7 +729,6 @@ static int armada_37xx_pinctrl_probe(struct udevice *dev)
if (!info->funcs) if (!info->funcs)
return -ENOMEM; return -ENOMEM;
ret = armada_37xx_fill_group(info); ret = armada_37xx_fill_group(info);
if (ret) if (ret)
return ret; return ret;

1
drivers/pinctrl/pinctrl-sti.c
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@ -208,7 +208,6 @@ void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
generic_clear_bit(bit, sysconfreg); generic_clear_bit(bit, sysconfreg);
} }
static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config) static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{ {
struct fdtdec_phandle_args args; struct fdtdec_phandle_args args;

1
drivers/pinctrl/pinctrl_pic32.c
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@ -114,7 +114,6 @@ struct pic32_reg_in_mux {
#define PPS_OUT(__port, __pin) \ #define PPS_OUT(__port, __pin) \
(((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2) (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
struct pic32_pinctrl_priv { struct pic32_pinctrl_priv {
struct pic32_reg_in_mux *mux_in; /* mux input function */ struct pic32_reg_in_mux *mux_in; /* mux input function */
struct pic32_reg_port *pinconf; /* pin configuration*/ struct pic32_reg_port *pinconf; /* pin configuration*/

1
drivers/pinctrl/renesas/pfc-r8a77951.c
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@ -250,7 +250,6 @@
#define GPSR7_1 FM(AVS2) #define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1) #define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

1
drivers/pinctrl/renesas/pfc-r8a7796.c
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@ -256,7 +256,6 @@
#define GPSR7_1 FM(AVS2) #define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1) #define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

1
drivers/pinctrl/renesas/pfc-r8a77965.c
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@ -256,7 +256,6 @@
#define GPSR7_1 FM(AVS2) #define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1) #define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

1
drivers/pinctrl/renesas/pfc-r8a77970.c
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@ -160,7 +160,6 @@
#define GPSR5_1 FM(QSPI0_MOSI_IO0) #define GPSR5_1 FM(QSPI0_MOSI_IO0)
#define GPSR5_0 FM(QSPI0_SPCLK) #define GPSR5_0 FM(QSPI0_SPCLK)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

1
drivers/pinctrl/renesas/pfc-r8a77980.c
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@ -194,7 +194,6 @@
#define GPSR5_1 FM(QSPI0_MOSI_IO0) #define GPSR5_1 FM(QSPI0_MOSI_IO0)
#define GPSR5_0 FM(QSPI0_SPCLK) #define GPSR5_0 FM(QSPI0_SPCLK)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

2
drivers/pinctrl/renesas/pfc-r8a77995.c
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@ -428,7 +428,6 @@ FM(IP12_31_28) IP12_31_28 \
#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
#define PINMUX_MOD_SELS \ #define PINMUX_MOD_SELS \
\ \
MOD_SEL1_31 \ MOD_SEL1_31 \
@ -2870,7 +2869,6 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ } { /* sentinel */ }
}; };
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{ {
switch (pin) { switch (pin) {

1
drivers/pinctrl/renesas/pfc-r8a779f0.c
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@ -654,7 +654,6 @@ static const unsigned int i2c5_mux[] = {
SDA5_MARK, SCL5_MARK, SDA5_MARK, SCL5_MARK,
}; };
/* - INTC-EX ---------------------------------------------------------------- */ /* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = { static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */ /* IRQ0 */

1
drivers/pinctrl/renesas/pfc-r8a779h0.c
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@ -261,7 +261,6 @@
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
/* SR0 */ /* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

1
drivers/pinctrl/renesas/pfc.c
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@ -947,7 +947,6 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
return 0; return 0;
} }
static int sh_pfc_pinctrl_probe(struct udevice *dev) static int sh_pfc_pinctrl_probe(struct udevice *dev)
{ {
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);

1
drivers/pinctrl/tegra/funcmux-tegra20.c
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@ -32,7 +32,6 @@ static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(SLXD, SPDIF, NORMAL, NORMAL), PINMUX(SLXD, SPDIF, NORMAL, NORMAL),
}; };
int funcmux_select(enum periph_id id, int config) int funcmux_select(enum periph_id id, int config)
{ {
int bad_config = config != FUNCMUX_DEFAULT; int bad_config = config != FUNCMUX_DEFAULT;