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board: freescale: t208xrdb: enable Power-On Reset for rev D boards

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Starting with board revision D, the MISCCSR CPLD register needs to be
configured to enable Power-on Reset for software reset commands.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Camelia Groza 2021-07-29 19:31:20 +03:00 committed by Priyanka Jain
parent 00ac37a9bc
commit 6466b95e7c
2 changed files with 11 additions and 0 deletions
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4
board/freescale/t208xrdb/cpld.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* Copyright 2014 Freescale Semiconductor * Copyright 2014 Freescale Semiconductor
* Copyright 2021 NXP
*/ */
/* /*
@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value);
/* RSTCON Register */ /* RSTCON Register */
#define CPLD_RSTCON_EDC_RST 0x04 #define CPLD_RSTCON_EDC_RST 0x04
/* MISCCSR Register */
#define CPLD_MISC_POR_EN 0x30

7
board/freescale/t208xrdb/t208xrdb.c
View File

@ -128,6 +128,13 @@ int misc_init_r(void)
reg |= CPLD_RSTCON_EDC_RST; reg |= CPLD_RSTCON_EDC_RST;
CPLD_WRITE(reset_ctl, reg); CPLD_WRITE(reset_ctl, reg);
/* Enable POR for boards revisions D and up */
if (get_hw_revision() >= 'D') {
reg = CPLD_READ(misc_csr);
reg |= CPLD_MISC_POR_EN;
CPLD_WRITE(misc_csr, reg);
}
return 0; return 0;
} }