mirror of
https://github.com/smaeul/u-boot.git
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board: cssi: Add MIAE & VGoIP devices
This adds support for the MIAE and VGoIP devices. Those devices have the same CPU board that the MCR3000_2G board. The devices are very modular, they are provided with interchangeable front and back panels. Linux kernel is shipped with a device tree which contains all possible setups, and U-boot eliminates unrelated nodes based on detected hardware. This patch was originally written by Charles Frey who's email address is not valid anymore as he left the company. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
This commit is contained in:
Christophe Leroy
parent
dac3c6f625
commit
6a8c36b936
@ -29,8 +29,16 @@ DECLARE_GLOBAL_DATA_PTR;
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#define BOARD_CMPC885 "cmpc885"
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#define BOARD_MCR3000_2G "mcr3k_2g"
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#define BOARD_VGOIP "vgoip"
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#define BOARD_MIAE "miae"
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#define TYPE_MCR 0x22
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#define TYPE_MIAE 0x23
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#define FAR_CASRSA 2
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#define FAR_VGOIP 4
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#define FAV_CLA 7
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#define FAV_SRSA 8
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#define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE)
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#define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2))
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@ -38,6 +46,12 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ADDR_FPGA_R_BASE ((unsigned char __iomem *)CONFIG_FPGA_BASE)
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#define ADDR_FPGA_R_ALARMES_IN ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x31)
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#define ADDR_FPGA_R_FAV ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44)
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#define PATH_PHY2 "/soc@ff000000/mdio@e00/ethernet-phy@2"
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#define PATH_PHY3 "/soc@ff000000/mdio@e00/ethernet-phy@3"
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#define PATH_ETH1 "/soc@ff000000/ethernet@1e00"
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#define FIBER_PHY PATH_PHY2
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#define FPGA_R_ACQ_AL_FAV 0x04
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#define R_ETAT_PRES_BASE 0x0040
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@ -45,15 +59,68 @@ DECLARE_GLOBAL_DATA_PTR;
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#define R_RESET_STATUS 0x0400
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#define R_RST_STATUS 0x0004
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static int fdt_set_node_and_value(void *blob, char *node, const char *prop,
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void *var, int size)
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{
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int ret, off;
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off = fdt_path_offset(blob, node);
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if (off < 0) {
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printf("Cannot find %s node err:%s\n", node, fdt_strerror(off));
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return off;
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}
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ret = fdt_setprop(blob, off, prop, var, size);
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if (ret < 0)
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printf("Cannot set %s/%s prop err: %s\n", node, prop, fdt_strerror(ret));
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return ret;
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}
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/* Checks front/rear id and remove unneeded nodes from the blob */
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static void ft_cleanup(void *blob, uint32_t id, const char *prop, const char *compatible)
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{
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int off;
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off = fdt_node_offset_by_compatible(blob, -1, compatible);
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while (off != -FDT_ERR_NOTFOUND) {
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const struct fdt_property *ids;
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int nb_ids, idx;
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int tmp = -1;
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ids = fdt_get_property(blob, off, prop, &nb_ids);
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for (idx = 0; idx < nb_ids; idx += 4) {
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if (*((uint32_t *)&ids->data[idx]) == id)
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break;
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}
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if (idx >= nb_ids)
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fdt_del_node(blob, off);
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else
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tmp = off;
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off = fdt_node_offset_by_compatible(blob, tmp, compatible);
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}
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fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t));
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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u8 fav_id, far_id;
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const char *sync = "receive";
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ft_cpu_setup(blob, bd);
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/* BRG */
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do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
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bd->bi_busfreq, 1);
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do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", bd->bi_busfreq, 1);
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/* MAC addr */
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fdt_fixup_ethernet(blob);
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@ -67,8 +134,33 @@ int ft_board_setup(void *blob, struct bd_info *bd)
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do_fixup_by_path_u32(blob, "/localbus/e1", "channel-phase", 0, 1);
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/* E1 interface - rising edge sync pulse transmit */
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do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse",
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sync, strlen(sync), 1);
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do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse", sync, strlen(sync), 1);
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/* MIAE only */
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if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) || in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE)
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return 0;
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far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
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ft_cleanup(blob, (u32)far_id, "far-id", "cs,mia-far");
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/*
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* special case, with CASRSA (far_id: 2)
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* FAV-SRSA register itself as FAV-CLA
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*/
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fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5;
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if (far_id == FAR_CASRSA && fav_id == FAV_CLA)
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fav_id = FAV_SRSA;
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ft_cleanup(blob, (u32)fav_id, "fav-id", "cs,mia-fav");
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if (far_id == FAR_CASRSA) {
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/* switch to phy3 with gpio, we'll only use phy3 */
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm;
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setbits_be32(&cp->cp_pedat, 0x00002000);
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}
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return 0;
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}
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@ -80,8 +172,18 @@ int checkboard(void)
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/* Is a motherboard present ? */
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if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
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switch (in_8(ADDR_FPGA_R_BASE)) {
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int far_id;
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case TYPE_MCR:
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printf("MCR3000_2G (CS GROUP)\n");
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break;
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case TYPE_MIAE:
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far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
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if (far_id == FAR_VGOIP)
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printf("VGoIP (CS GROUP)\n");
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else
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printf("MIAE (CS GROUP)\n");
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break;
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default:
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printf("Unknown\n");
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@ -149,7 +251,8 @@ static int setup_mac(void)
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int misc_init_r(void)
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{
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u8 val;
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u8 val, tmp, far_id;
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int count = 3;
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val = in_8(ADDR_FPGA_R_BASE);
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@ -165,6 +268,31 @@ int misc_init_r(void)
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env_set("config", BOARD_MCR3000_2G);
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env_set("hostname", BOARD_MCR3000_2G);
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break;
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case TYPE_MIAE:
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do {
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tmp = in_8(ADDR_FPGA_R_BASE + 0x41);
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count--;
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mdelay(10); /* 10msec wait */
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} while (count && tmp != in_8(ADDR_FPGA_R_BASE + 0x41));
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if (!count) {
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printf("Cannot read the reset factory switch position\n");
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hang();
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}
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if (tmp & 0x1)
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env_set_default("Factory settings switch ON", 0);
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env_set("config", BOARD_MIAE);
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far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
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if (far_id == FAR_VGOIP)
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env_set("hostname", BOARD_VGOIP);
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else
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env_set("hostname", BOARD_MIAE);
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break;
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default:
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env_set("config", BOARD_CMPC885);
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env_set("hostname", BOARD_CMPC885);
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@ -488,6 +616,150 @@ static void iop_setup_cmpc885(void)
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clrbits_be32(&cp->cp_peso, 0x00031980);
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}
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static void iop_setup_miae(void)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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iop8xx_t __iomem *iop = &immr->im_ioport;
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cpm8xx_t __iomem *cp = &immr->im_cpm;
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/* Wait reset on FPGA_F */
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udelay(100);
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/* Set the front panel LED color to red */
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clrbits_8(ADDR_FPGA_R_FAV, 0x02);
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/* We must initialize data before changing direction */
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setbits_be16(&iop->iop_pcdat, 0x0888);
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setbits_be16(&iop->iop_pddat, 0x0201);
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setbits_be32(&cp->cp_pbdat, 0x00021510);
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setbits_be32(&cp->cp_pedat, 0x00000002);
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/*
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* PAPAR[13] = 1 [0x0004] -> GPIO: (RXD2)
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* PAPAR[12] = 1 [0x0008] -> GPIO: (TXD2)
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* PAPAR[9] = 1 [0x0040] -> GPIO: (TDM1O)
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* PAPAR[8] = 1 [0x0080] -> GPIO: (TDM1I)
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* PAPAR[7] = 1 [0x0100] -> GPIO: (TDM_BCLK_MPC)
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* PAPAR[6] = 1 [0x0200] -> GPIO: (CLK2)
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*/
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setbits_be16(&iop->iop_papar, 0x03CC);
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/*
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* PBODR[16] = 0 [0x00008000] -> GPIO: (L1ST4)
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*/
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clrbits_be16(&cp->cp_pbodr, 0x00008000);
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/*
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* PBDIR[27] = 1 [0x00000010] -> GPIO: (WR_TEMP2)
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* PBDIR[26] = 1 [0x00000020] -> GPIO: (BRG02)
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* PBDIR[23] = 1 [0x00000100] -> GPIO: (CS_TEMP2)
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* PBDIR[18] = 1 [0x00002000] -> GPIO: (RTS2)
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* PBDIR[16] = 0 [0x00008000] -> GPIO: (L1ST4)
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* PBDIR[15] = 1 [0x00010000] -> GPIO: (BRG03)
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* PBDIR[14] = 1 [0x00020000] -> GPIO: (CS_TEMP)
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*/
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clrsetbits_be32(&cp->cp_pbdir, 0x0003A130, 0x00032130);
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/*
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* PBPAR[20] = 1 [0x00000800] -> GPIO: (SMRXD2)
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* PBPAR[17] = 1 [0x00004000] -> GPIO: (L1ST3)
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* PBPAR[16] = 1 [0x00008000] -> GPIO: (L1ST4)
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*/
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setbits_be32(&cp->cp_pbpar, 0x0000C800);
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/*
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* PCPAR[14] = 1 [0x0002] -> GPIO: (L1ST2)
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*/
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setbits_be16(&iop->iop_pcpar, 0x0002);
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/*
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* PDPAR[14] = 1 [0x0002] -> GPIO: (TDM_FS_MPC)
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* PDPAR[11] = 1 [0x0010] -> GPIO: (RXD3)
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* PDPAR[10] = 1 [0x0020] -> GPIO: (TXD3)
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* PDPAR[9] = 1 [0x0040] -> GPIO: (TXD4)
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* PDPAR[7] = 1 [0x0100] -> GPIO: (RTS3)
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* PDPAR[5] = 1 [0x0400] -> GPIO: (CLK8)
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* PDPAR[3] = 1 [0x1000] -> GPIO: (CLK7)
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*/
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setbits_be16(&iop->iop_pdpar, 0x1572);
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/*
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* PEPAR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
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* PEPAR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
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* PEPAR[25] = 1 [0x00000040] -> GPIO: (RXD4)
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* PEPAR[24] = 1 [0x00000080] -> GPIO: (BRG01)
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* PEPAR[23] = 1 [0x00000100] -> GPIO: (L1ST1)
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* PEPAR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
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* PEPAR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
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* PEPAR[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
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* PEPAR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
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* PEPAR[17] = 1 [0x00004000] -> GPIO: (CLK5)
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* PEPAR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
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* PEPAR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
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* PEPAR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
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*/
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setbits_be32(&cp->cp_pepar, 0x0003DFF0);
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/*
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* PADIR[9] = 1 [0x0040] -> GPIO: (TDM1O)
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* PADIR[8] = 1 [0x0080] -> GPIO: (TDM1I)
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* PADIR[5] = 0 [0x0400] -> GPIO: ()
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*/
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clrsetbits_be16(&iop->iop_padir, 0x04C0, 0x00C0);
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/*
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* PCDIR[15] = 1 [0x0001] -> GPIO: (WP_EEPROM2)
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* PCDIR[14] = 1 [0x0002] -> GPIO: (L1ST2)
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* PCDIR[13] = 0 [0x0004] -> GPIO: ()
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* PCDIR[12] = 1 [0x0008] -> GPIO: (CS_EEPROM2)
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* PCDIR[8] = 1 [0x0080] -> GPIO: (CS_CODEC_2)
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* PCDIR[4] = 1 [0x0800] -> GPIO: (CS_CODEC_1)
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*/
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clrsetbits_be16(&iop->iop_pcdir, 0x088F, 0x088B);
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/*
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* PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
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* PDDIR[6] = 1 [0x0200] -> GPIO: (CS_CODEC_3)
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*/
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setbits_be16(&iop->iop_pddir, 0x0240);
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/*
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* PEDIR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
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* PEDIR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
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* PEDIR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
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* PEDIR[23] = 1 [0x00000100] -> GPIO: (L1ST1)
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* PEDIR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
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* PEDIR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
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* PEDIR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
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* PEDIR[18] = 1 [0x00002000] -> GPIO: (PE18)
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* PEDIR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
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* PEDIR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
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* PEDIR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
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*/
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setbits_be32(&cp->cp_pedir, 0x0003B732);
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/*
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* PAODR[10] = 1 [0x0020] -> GPIO: (INIT_FPGA_F)
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*/
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setbits_be16(&iop->iop_paodr, 0x0020);
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/*
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* PEODR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
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* PEODR[18] = 0 [0x00002000] -> GPIO: (PE18)
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*/
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clrsetbits_be32(&cp->cp_peodr, 0x00002002, 0x00000002);
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/*
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* PESO[24] = 1 [0x00000080] -> GPIO: (BRG01)
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* PESO[23] = 1 [0x00000100] -> GPIO: (L1ST1)
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* PESO[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
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* PESO[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
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* PESO[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
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* PESO[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
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*/
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setbits_be32(&cp->cp_peso, 0x00031980);
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}
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int board_early_init_f(void)
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{
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return 0;
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@ -818,6 +1090,10 @@ int board_early_init_r(void)
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iop_setup_mcr();
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break;
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case TYPE_MIAE:
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iop_setup_miae();
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break;
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default:
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break;
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}
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