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Merge tag 'u-boot-rockchip-20250301' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/2489

- Fix SD-Card boot on rk3308-rock-s0 v1.1;
- Fix crash on nanopi-r4s seconde usb port;
- Disable undeeded PCI config for nanopi-r3s-rk3566
- Correct usage of IS_ENABLED()
This commit is contained in:
Tom Rini 2025-03-01 07:51:14 -06:00
commit 6ae0a578de
6 changed files with 23 additions and 5 deletions
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12
arch/arm/dts/rk3308-rock-s0-u-boot.dtsi
View File

@ -7,6 +7,14 @@
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
};
&sdmmc_2030 {
bootph-pre-ram;
};
&uart0 {
bootph-all;
clock-frequency = <24000000>;
@ -16,6 +24,10 @@
bootph-all;
};
&vcc_sd {
bootph-pre-ram;
};
&vdd_core {
regulator-init-microvolt = <1015000>;
};

5
arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
View File

@ -36,3 +36,8 @@
};
};
};
&u2phy1_host {
phy-supply = <&vdd_5v>;
status = "okay";
};

1
configs/nanopi-r3s-rk3566_defconfig
View File

@ -54,7 +54,6 @@ CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_RTL8169=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y

2
configs/rock-s0-rk3308_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-s0"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
@ -53,6 +54,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_BAUDRATE=1500000

4
drivers/clk/rockchip/clk_rk3568.c
View File

@ -2680,7 +2680,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
return ret;
};
#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
#if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))
static int rk3568_gmac0_src_set_parent(struct clk *clk, struct clk *parent)
{
struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
@ -2859,7 +2859,7 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
static struct clk_ops rk3568_clk_ops = {
.get_rate = rk3568_clk_get_rate,
.set_rate = rk3568_clk_set_rate,
#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
#if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))
.set_parent = rk3568_clk_set_parent,
#endif
};

4
drivers/clk/rockchip/clk_rk3588.c
View File

@ -1822,7 +1822,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
*/
#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
#if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))
static int __maybe_unused rk3588_dclk_vop_set_parent(struct clk *clk,
struct clk *parent)
{
@ -1915,7 +1915,7 @@ static int rk3588_clk_set_parent(struct clk *clk, struct clk *parent)
static struct clk_ops rk3588_clk_ops = {
.get_rate = rk3588_clk_get_rate,
.set_rate = rk3588_clk_set_rate,
#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
#if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))
.set_parent = rk3588_clk_set_parent,
#endif
};