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Merge tag 'u-boot-imx-master-20240802' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21846

- Convert warp7 to OF_UPSTREAM.
- Add 'cpu' command to imx8m and imx93.
- Enable CMD_ERASEENV for imx8mm/mp Phytec boards.
This commit is contained in:
Tom Rini 2024-08-02 14:40:59 -06:00
commit 6becf9ba1a
24 changed files with 266 additions and 511 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MAINTAINERS
View File

@ -997,6 +997,13 @@ F: arch/m68k/
F: doc/arch/m68k.rst
F: drivers/watchdog/mcf_wdt.c
CPU
M: Simon Glass <sjg@chromium.org>
M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
S: Maintained
F: cmd/cpu.c
F: doc/usage/cpu.rst
CYCLIC
M: Stefan Roese <sr@denx.de>
S: Maintained

1
arch/arm/dts/Makefile
View File

@ -883,7 +883,6 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7-cm.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7s-warp.dtb \
imx7d-meerkat96.dtb \
imx7d-pico-pi.dtb \
imx7d-pico-hobbit.dtb \

500
arch/arm/dts/imx7s-warp.dts
View File

@ -1,500 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 NXP Semiconductors.
* Author: Fabio Estevam <fabio.estevam@nxp.com>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx7s.dtsi"
/ {
model = "Element14 Warp i.MX7 Board";
compatible = "element14,imx7s-warp", "fsl,imx7s";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio>;
autorepeat;
back {
label = "Back";
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_BACK>;
wakeup-source;
};
};
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_reg>;
regulator-name = "brcm_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
reg_bt: regulator-bt {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_reg>;
enable-active-high;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
regulator-name = "bt_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_peri_3p15v: regulator-peri-3p15v {
compatible = "regulator-fixed";
regulator-name = "peri_3p15v_reg";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
&clks {
assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <884736000>;
};
&csi {
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov2680: camera@36 {
compatible = "ovti,ov2680";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov2680>;
reg = <0x36>;
clocks = <&osc>;
clock-names = "xvclk";
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
DOVDD-supply = <&sw2_reg>;
DVDD-supply = <&sw2_reg>;
AVDD-supply = <&reg_peri_3p15v>;
port {
ov2680_to_mipi: endpoint {
remote-endpoint = <&mipi_from_sensor>;
clock-lanes = <0>;
data-lanes = <1>;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: sgtl5000@a {
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
VDDA-supply = <&vgen4_reg>;
VDDIO-supply = <&vgen4_reg>;
VDDD-supply = <&vgen2_reg>;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
};
&mipi_csi {
clock-frequency = <166000000>;
status = "okay";
ports {
port@0 {
reg = <0>;
mipi_from_sensor: endpoint {
remote-endpoint = <&ov2680_to_mipi>;
data-lanes = <1>;
};
};
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
<&clks IMX7D_SAI1_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <36864000>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
uart-has-rtscts;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
fsl,dte-mode;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
keep-power-in-suspend;
no-1-8-v;
non-removable;
vmmc-supply = <&reg_brcm>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
no-1-8-v;
fsl,tuning-step = <2>;
non-removable;
status = "okay";
};
&video_mux {
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
>;
};
pinctrl_bt_reg: btreggrp {
fsl,pins = <
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
>;
};
pinctrl_ov2680: ov2660grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
>;
};
pinctrl_sai1_mclk: sai1mclkgrp {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
>;
};
};
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};

1
arch/arm/mach-imx/mx7/Kconfig
View File

@ -87,6 +87,7 @@ config TARGET_WARP7
select DM_THERMAL
select MX7D
imply CMD_DM
imply OF_UPSTREAM
config TARGET_COLIBRI_IMX7
bool "Support Colibri iMX7S/iMX7D modules"

44
cmd/cpu.c
View File

@ -3,6 +3,7 @@
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
* Copyright (c) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright 2024 NXP
*/
#include <command.h>
@ -18,6 +19,19 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
"Device ID",
};
static struct udevice *cpu_find_device(unsigned long cpu_id)
{
struct udevice *dev;
for (uclass_first_device(UCLASS_CPU, &dev); dev;
uclass_next_device(&dev)) {
if (cpu_id == dev_seq(dev))
return dev;
}
return NULL;
}
static int print_cpu_list(bool detail)
{
struct udevice *dev;
@ -82,10 +96,36 @@ static int do_cpu_detail(struct cmd_tbl *cmdtp, int flag, int argc,
return 0;
}
static int do_cpu_release(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct udevice *dev;
unsigned long cpu_id;
unsigned long long boot_addr;
if (argc != 3)
return CMD_RET_USAGE;
cpu_id = dectoul(argv[1], NULL);
dev = cpu_find_device(cpu_id);
if (!dev)
return CMD_RET_FAILURE;
boot_addr = simple_strtoull(argv[2], NULL, 16);
if (cpu_release_core(dev, boot_addr))
return CMD_RET_FAILURE;
return 0;
}
U_BOOT_LONGHELP(cpu,
"list - list available CPUs\n"
"cpu detail - show CPU detail");
"cpu detail - show CPU detail\n"
"cpu release <core ID> <addr> - Release CPU <core ID> at <addr>\n"
" <core ID>: the sequence number in list subcommand outputs");
U_BOOT_CMD_WITH_SUBCMDS(cpu, "display information about CPUs", cpu_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_cpu_list),
U_BOOT_SUBCMD_MKENT(detail, 1, 0, do_cpu_detail));
U_BOOT_SUBCMD_MKENT(detail, 1, 0, do_cpu_detail),
U_BOOT_SUBCMD_MKENT(release, 3, 0, do_cpu_release));

1
configs/imx8mm-phygate-tauri-l_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2

3
configs/imx8mm_evk_defconfig
View File

@ -118,3 +118,6 @@ CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
CONFIG_CPU=y
CONFIG_CPU_IMX=y
CONFIG_CMD_CPU=y

3
configs/imx8mn_evk_defconfig
View File

@ -105,3 +105,6 @@ CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_WATCHDOG=y
CONFIG_CPU=y
CONFIG_CPU_IMX=y
CONFIG_CMD_CPU=y

3
configs/imx8mp_evk_defconfig
View File

@ -137,3 +137,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_IMX_WATCHDOG=y
CONFIG_CPU=y
CONFIG_CPU_IMX=y
CONFIG_CMD_CPU=y

1
configs/imx93_11x11_evk_defconfig
View File

@ -52,6 +52,7 @@ CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_CPU=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y

11
configs/phycore-imx8mm_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@ -23,6 +24,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
@ -48,6 +50,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
@ -59,6 +62,7 @@ CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -110,10 +114,15 @@ CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_IMX=y
CONFIG_PHY=y
CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y

1
configs/phycore-imx8mp_defconfig
View File

@ -52,6 +52,7 @@ CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2

2
configs/warp7_bl33_defconfig
View File

@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7s-warp"
CONFIG_TARGET_WARP7=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y

2
configs/warp7_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7s-warp"
CONFIG_TARGET_WARP7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set

101
doc/usage/cmd/cpu.rst Normal file
View File

@ -0,0 +1,101 @@
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2024 NXP
.. index::
single: cpu (command)
cpu command
===========
Synopsis
--------
::
cpu list
cpu detail
cpu release <core ID> <addr>
Description
-----------
The *cpu* command prints information about the CPUs, and release a CPU core
to a given address to run applications.
cpu list
~~~~~~~~
The 'list' subcommand lists and prints brief information of all the CPU cores,
the CPU information is provided by vendors' CPU driver.
cpu detail
~~~~~~~~~~
The 'detail' subcommand prints more details about the CPU cores, including
CPU ID, core frequency and feature list.
cpu release
~~~~~~~~~~~
The 'release' subcommand is used to release a CPU core to run a baremetal or
RTOS applications.
The parameter <core ID> is the sequence number of the CPU core to release.
The parameter <addr> is the address to run of the specified core after release.
Examples
--------
cpu list
~~~~~~~~
This example lists all the CPU cores On i.MX8M Plus EVK:
::
u-boot=> cpu list
0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
cpu detail
~~~~~~~~~~
This example prints the details of the CPU cores On i.MX8M Plus EVK:
::
u-boot=> cpu detail
0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
ID = 0, freq = 1.2 GHz: L1 cache, MMU
1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
ID = 0, freq = 1.2 GHz: L1 cache, MMU
2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
ID = 0, freq = 1.2 GHz: L1 cache, MMU
3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
ID = 0, freq = 1.2 GHz: L1 cache, MMU
cpu release
~~~~~~~~~~~
This example shows release the LAST CPU core to run a RTOS application, on
i.MX8M Plus EVK:
::
u-boot=> load mmc 1:2 c0000000 /hello_world.bin
66008 bytes read in 5 ms (12.6 MiB/s)
u-boot=> dcache flush; icache flush
u-boot=> cpu release 3 c0000000
Released CPU core (mpidr: 0x3) to address 0xc0000000
Configuration
-------------
The cpu command is available if CONFIG_CMD_CPU=y.
Return code
-----------
The return value $? is set to 0 (true) if the command is successful,
1 (false) otherwise.

1
doc/usage/index.rst
View File

@ -50,6 +50,7 @@ Shell commands
cmd/coninfo
cmd/conitrace
cmd/cp
cmd/cpu
cmd/cyclic
cmd/dm
cmd/ebtupdate

8
drivers/clk/imx/clk-imx8mm.c
View File

@ -21,6 +21,8 @@ static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@ -417,6 +419,12 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
#endif
clk_dm(IMX8MM_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
imx8mm_arm_core_sels,
ARRAY_SIZE(imx8mm_arm_core_sels),
CLK_IS_CRITICAL));
return 0;
}

8
drivers/clk/imx/clk-imx8mn.c
View File

@ -23,6 +23,8 @@ static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@ -403,6 +405,12 @@ static int imx8mn_clk_probe(struct udevice *dev)
imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
#endif
clk_dm(IMX8MN_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
imx8mn_arm_core_sels,
ARRAY_SIZE(imx8mn_arm_core_sels),
CLK_IS_CRITICAL));
return 0;
}

8
drivers/clk/imx/clk-imx8mp.c
View File

@ -21,6 +21,8 @@ static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@ -354,6 +356,12 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MP_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
imx8mp_arm_core_sels,
ARRAY_SIZE(imx8mp_arm_core_sels),
CLK_IS_CRITICAL));
return 0;
}

10
drivers/cpu/cpu-uclass.c
View File

@ -104,6 +104,16 @@ int cpu_get_vendor(const struct udevice *dev, char *buf, int size)
return ops->get_vendor(dev, buf, size);
}
int cpu_release_core(const struct udevice *dev, phys_addr_t addr)
{
struct cpu_ops *ops = cpu_get_ops(dev);
if (!ops->release_core)
return -ENOSYS;
return ops->release_core(dev, addr);
}
U_BOOT_DRIVER(cpu_bus) = {
.name = "cpu_bus",
.id = UCLASS_SIMPLE_BUS,

6
drivers/cpu/cpu_sandbox.c
View File

@ -44,6 +44,11 @@ void cpu_sandbox_set_current(const char *name)
cpu_current = name;
}
static int cpu_sandbox_release_core(const struct udevice *dev, phys_addr_t addr)
{
return 0;
}
static int cpu_sandbox_is_current(struct udevice *dev)
{
if (!strcmp(dev->name, cpu_current))
@ -58,6 +63,7 @@ static const struct cpu_ops cpu_sandbox_ops = {
.get_count = cpu_sandbox_get_count,
.get_vendor = cpu_sandbox_get_vendor,
.is_current = cpu_sandbox_is_current,
.release_core = cpu_sandbox_release_core,
};
static int cpu_sandbox_bind(struct udevice *dev)

38
drivers/cpu/imx8_cpu.c
View File

@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019, 2024 NXP
*/
#include <cpu.h>
#include <dm.h>
#include <thermal.h>
#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <firmware/imx/sci/sci.h>
#include <asm/arch/sys_proto.h>
@ -15,6 +16,7 @@
#include <imx_thermal.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/psci.h>
DECLARE_GLOBAL_DATA_PTR;
@ -31,6 +33,12 @@ struct cpu_imx_plat {
static const char *get_imx_type_str(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_IMX8MM:
return "8MM";
case MXC_CPU_IMX8MN:
return "8MN";
case MXC_CPU_IMX8MP:
return "8MP";
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "8QXP";
@ -184,8 +192,6 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
ret = snprintf(buf, size, " - invalid sensor data");
}
snprintf(buf + ret, size - ret, "\n");
return 0;
}
@ -193,7 +199,7 @@ static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
info->cpu_freq = plat->freq_mhz * 1000;
info->cpu_freq = plat->freq_mhz * 1000000;
info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
return 0;
}
@ -236,12 +242,34 @@ static int cpu_imx_is_current(struct udevice *dev)
return 0;
}
static int cpu_imx_release_core(const struct udevice *dev, phys_addr_t addr)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
struct pt_regs regs;
regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
regs.regs[1] = plat->mpidr;
regs.regs[2] = addr;
regs.regs[3] = 0;
smc_call(&regs);
if (regs.regs[0]) {
printf("Failed to release CPU core (mpidr: 0x%x)\n", plat->mpidr);
return -1;
}
printf("Released CPU core (mpidr: 0x%x) to address 0x%llx\n", plat->mpidr, addr);
return 0;
}
static const struct cpu_ops cpu_imx_ops = {
.get_desc = cpu_imx_get_desc,
.get_info = cpu_imx_get_info,
.get_count = cpu_imx_get_count,
.get_vendor = cpu_imx_get_vendor,
.is_current = cpu_imx_is_current,
.release_core = cpu_imx_release_core,
};
static const struct udevice_id cpu_imx_ids[] = {
@ -287,7 +315,7 @@ static int imx_cpu_probe(struct udevice *dev)
cpurev = get_cpu_rev();
plat->cpurev = cpurev;
plat->rev = get_imx_rev_str(cpurev & 0xFFF);
plat->type = get_imx_type_str((cpurev & 0xFF000) >> 12);
plat->type = get_imx_type_str((cpurev & 0x1FF000) >> 12);
plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000;
plat->mpidr = dev_read_addr(dev);
if (plat->mpidr == FDT_ADDR_T_NONE) {

15
include/cpu.h
View File

@ -102,6 +102,15 @@ struct cpu_ops {
* if not.
*/
int (*is_current)(struct udevice *dev);
/**
* release_core() - Relase a CPU core to the given address to run application
*
* @dev: Device to check (UCLASS_CPU)
* @addr: Address to relese the CPU core
* @return 0 if OK, -ve on error
*/
int (*release_core)(const struct udevice *dev, phys_addr_t addr);
};
#define cpu_get_ops(dev) ((struct cpu_ops *)(dev)->driver->ops)
@ -164,4 +173,10 @@ int cpu_is_current(struct udevice *cpu);
*/
struct udevice *cpu_get_current_dev(void);
/**
* cpu_release_core() - Relase a CPU core to the given address to run application
*
* @return 0 if OK, -ve on error
*/
int cpu_release_core(const struct udevice *dev, phys_addr_t addr);
#endif

2
test/dm/cpu.c
View File

@ -43,6 +43,8 @@ static int dm_test_cpu(struct unit_test_state *uts)
ut_assertok(cpu_get_vendor(dev, text, sizeof(text)));
ut_assertok(strcmp(text, "Languid Example Garbage Inc."));
ut_assertok(cpu_release_core(dev, 0));
return 0;
}