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nxp: ls1046ardb: Convert README to rST
This converts the readme for this board to rST. I have tried not to change any semantics from the original (though I did convert MB to M). Signed-off-by: Sean Anderson <sean.anderson@seco.com>
This commit is contained in:
Sean Anderson
Tom Rini
parent
d0ed9b1081
commit
71230cdaa9
@ -14,3 +14,4 @@ F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
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F: doc/board/nxp/ls1046ardb.rst
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@ -1,76 +0,0 @@
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Overview
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--------
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The LS1046A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The LS1046ARDB provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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LS1046ARDB board Overview
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-----------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: 10GBase-R with x1 RJ45 connector
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- Lane1: 10GBase-R Cage
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- Lane2: SGMII.5
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- Lane3: SGMII.6
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: PCIe1 with miniPCIe slot
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- Lane1: PCIe2 with PCIe x2 slot
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- Lane2: PCIe3 with PCIe x4 slot
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- Lane3: SATA
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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-IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- one Type A port, one Micro-AB port
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
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0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
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0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
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0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
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0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
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0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
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0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
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0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
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0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
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QSPI flash map:
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Start Address End Address Description Size
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0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
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0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
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0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
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0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
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0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
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+ bootscript 3MB
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0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
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0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
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0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB
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0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
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Booting Options
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---------------
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a) QSPI boot
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b) SD boot
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c) eMMC boot
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@ -13,6 +13,7 @@ NXP Semiconductors
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imx8qxp_mek
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imx8qxp_mek
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imxrt1020-evk
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imxrt1020-evk
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imxrt1050-evk
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imxrt1050-evk
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ls1046ardb
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mx6sabreauto
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mx6sabreauto
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mx6sabresd
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mx6sabresd
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mx6ul_14x14_evk
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mx6ul_14x14_evk
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100
doc/board/nxp/ls1046ardb.rst
Normal file
100
doc/board/nxp/ls1046ardb.rst
Normal file
@ -0,0 +1,100 @@
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.. SPDX-License-Identifier: GPL-2.0+
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LS1046ARDB
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==========
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The LS1046A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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|
LayerScape Architecture processor. The LS1046ARDB provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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LS1046ARDB board Overview
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-------------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: 10GBase-R with x1 RJ45 connector
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- Lane1: 10GBase-R Cage
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- Lane2: SGMII.5
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- Lane3: SGMII.6
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: PCIe1 with miniPCIe slot
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- Lane1: PCIe2 with PCIe x2 slot
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- Lane2: PCIe3 with PCIe x4 slot
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- Lane3: SATA
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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- IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- one Type A port, one Micro-AB port
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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================== ================== ================ =====
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Start Address End Address Description Size
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================== ================== ================ =====
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``0x00_0000_0000`` ``0x00_000F_FFFF`` Secure Boot ROM 1M
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``0x00_0100_0000`` ``0x00_0FFF_FFFF`` CCSRBAR 240M
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``0x00_1000_0000`` ``0x00_1000_FFFF`` OCRAM0 64K
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``0x00_1001_0000`` ``0x00_1001_FFFF`` OCRAM1 64K
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``0x00_2000_0000`` ``0x00_20FF_FFFF`` DCSR 16M
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``0x00_7E80_0000`` ``0x00_7E80_FFFF`` IFC - NAND Flash 64K
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``0x00_7FB0_0000`` ``0x00_7FB0_0FFF`` IFC - CPLD 4K
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``0x00_8000_0000`` ``0x00_FFFF_FFFF`` DRAM1 2G
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``0x05_0000_0000`` ``0x05_07FF_FFFF`` QMAN S/W Portal 128M
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``0x05_0800_0000`` ``0x05_0FFF_FFFF`` BMAN S/W Portal 128M
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``0x08_8000_0000`` ``0x09_FFFF_FFFF`` DRAM2 6G
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``0x40_0000_0000`` ``0x47_FFFF_FFFF`` PCI Express1 32G
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``0x48_0000_0000`` ``0x4F_FFFF_FFFF`` PCI Express2 32G
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``0x50_0000_0000`` ``0x57_FFFF_FFFF`` PCI Express3 32G
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================== ================== ================ =====
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QSPI flash map
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--------------
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================== ================== ================== =====
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Start Address End Address Description Size
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================== ================== ================== =====
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``0x00_4000_0000`` ``0x00_400F_FFFF`` RCW + PBI 1M
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``0x00_4010_0000`` ``0x00_402F_FFFF`` U-Boot 2M
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``0x00_4030_0000`` ``0x00_403F_FFFF`` U-Boot Env 1M
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``0x00_4040_0000`` ``0x00_405F_FFFF`` PPA 2M
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``0x00_4060_0000`` ``0x00_408F_FFFF`` Secure boot header 3M
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+ bootscript
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``0x00_4090_0000`` ``0x00_4093_FFFF`` FMan ucode 256K
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``0x00_4094_0000`` ``0x00_4097_FFFF`` QE/uQE firmware 256K
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``0x00_4098_0000`` ``0x00_40FF_FFFF`` Reserved 6M
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``0x00_4100_0000`` ``0x00_43FF_FFFF`` FIT Image 48M
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================== ================== ================== =====
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Booting Options
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---------------
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- QSPI boot
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- SD boot
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- eMMC boot
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