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board: riscv: Sort target configs alphabetically

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Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2021-08-07 12:09:35 -05:00
parent 45f2d10154
commit 75207ede77
1 changed files with 4 additions and 4 deletions
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8
arch/riscv/Kconfig
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@ -14,6 +14,9 @@ config TARGET_AX25_AE350
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
@ -28,9 +31,6 @@ config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
select SYS_CACHE_SHIFT_6
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
endchoice
config SYS_ICACHE_OFF
@ -61,9 +61,9 @@ config SPL_SYS_DCACHE_OFF
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below