mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
Fix LOWBOOT configuration for MPC5200 with DDR memory
This commit is contained in:
wdenk
parent
f8d813e34f
commit
79d696fc55
@ -2,6 +2,8 @@
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Changes for U-Boot 1.0.2:
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======================================================================
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* Fix LOWBOOT configuration for MPC5200 with DDR memory
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* Fix SDRAM timings for LITE5200 / IceCube board
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* Handle Auti-MDIX / connection status for INCA-IP
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3
Makefile
3
Makefile
@ -207,9 +207,10 @@ PATI_config:unconfig
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MPC5200LITE_config \
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MPC5200LITE_LOWBOOT_config \
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MPC5200LITE_LOWBOOT08_config \
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icecube_5200_DDR_LOWBOOT_config \
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icecube_5200_DDR_config \
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IceCube_5200_DDR_config \
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icecube_5200_DDR_LOWBOOT_config \
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icecube_5200_DDR_LOWBOOT08_config \
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icecube_5200_config \
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IceCube_5200_config \
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IceCube_5100_config: unconfig
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@ -108,18 +108,19 @@ boot_warm:
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#error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
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#endif /* CFG_RAMBOOT */
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lis r4, CFG_DEFAULT_MBAR@h
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lis r3, 0x0000FF00@h
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ori r3, r3, 0x0000FF00@l
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stw r3, 0x4(r4)
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lis r3, 0x0000FFFF@h
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ori r3, r3, 0x0000FFFF@l
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stw r3, 0x8(r4)
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lis r3, START_REG(CFG_BOOTCS_START)@h
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ori r3, r3, START_REG(CFG_BOOTCS_START)@l
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stw r3, 0x4(r4) /* CS0 start */
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lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
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ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
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stw r3, 0x8(r4) /* CS0 stop */
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lis r3, 0x00047800@h
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ori r3, r3, 0x00047800@l
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stw r3, 0x300(r4)
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stw r3, 0x300(r4) /* set timing, CS0/boot conf reg */
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lis r3, 0x02010000@h
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ori r3, r3, 0x02010000@l
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stw r3, 0x54(r4)
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stw r3, 0x54(r4) /* CS0 and Boot enable, IPBI ctrl reg */
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lis r3, lowboot_reentry@h
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ori r3, r3, lowboot_reentry@l
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@ -127,18 +128,18 @@ boot_warm:
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blr /* jump to flash based address */
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lowboot_reentry:
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lis r3, 0x0000FF00@h
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ori r3, r3, 0x0000FF00@l
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stw r3, 0x4c(r4)
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lis r3, 0x0000FFFF@h
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ori r3, r3, 0x0000FFFF@l
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stw r3, 0x50(r4)
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lis r3, START_REG(CFG_BOOTCS_START)@h
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ori r3, r3, START_REG(CFG_BOOTCS_START)@l
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stw r3, 0x4c(r4) /* Boot start */
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lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
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ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
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stw r3, 0x50(r4) /* Boot stop */
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lis r3, 0x00047800@h
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ori r3, r3, 0x00047800@l
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stw r3, 0x300(r4)
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stw r3, 0x300(r4) /* set timing, CS0/boot conf reg */
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lis r3, 0x02000001@h
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ori r3, r3, 0x02000001@l
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stw r3, 0x54(r4)
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stw r3, 0x54(r4) /* Boot enable, CS0 disable, wait state enable */
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#endif /* CFG_LOWBOOT */
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#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
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@ -488,7 +488,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
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if (ohci->ed_controltail == NULL) {
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writel (ed, &ohci->regs->ed_controlhead);
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} else {
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ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 (ed);
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ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
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}
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ed->ed_prev = ohci->ed_controltail;
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if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
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@ -504,7 +504,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
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if (ohci->ed_bulktail == NULL) {
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writel (ed, &ohci->regs->ed_bulkhead);
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} else {
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ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 (ed);
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ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
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}
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ed->ed_prev = ohci->ed_bulktail;
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if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
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@ -598,7 +598,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
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ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
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/* dummy td; end of td list for ed */
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td = td_alloc (usb_dev);
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ed->hwTailP = ohci_cpu_to_le32 (td);
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ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
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ed->hwHeadP = ed->hwTailP;
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ed->state = ED_UNLINK;
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ed->type = usb_pipetype (pipe);
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@ -656,12 +656,12 @@ static void td_fill (ohci_t *ohci, unsigned int info,
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data = 0;
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td->hwINFO = ohci_cpu_to_le32 (info);
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td->hwCBP = ohci_cpu_to_le32 (data);
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td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
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if (data)
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td->hwBE = ohci_cpu_to_le32 (data + len - 1);
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td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
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else
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td->hwBE = 0;
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td->hwNextTD = ohci_cpu_to_le32 (td_pt);
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td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
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td->hwPSW [0] = ohci_cpu_to_le16 (((__u32)data & 0x0FFF) | 0xE000);
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/* append to queue */
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@ -14,7 +14,7 @@
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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@ -45,27 +45,27 @@
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#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
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#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
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#define SW_WRITE_REG(reg, value) \
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*((volatile u32*)reg) = (u32)value;\
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DELAY;\
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*((volatile u32*)reg) = (u32)value;
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*((volatile u32*)reg) = (u32)value;\
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DELAY;\
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*((volatile u32*)reg) = (u32)value;
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#define SW_READ_REG(reg, value) \
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value = (u32)*((volatile u32*)reg);\
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DELAY;\
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value = (u32)*((volatile u32*)reg);
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#define SW_READ_REG(reg, value) \
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value = (u32)*((volatile u32*)reg);\
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DELAY;\
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value = (u32)*((volatile u32*)reg);
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#define INCA_DMA_TX_POLLING_TIME 0x07
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#define INCA_DMA_RX_POLLING_TIME 0x07
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#define INCA_DMA_TX_POLLING_TIME 0x07
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#define INCA_DMA_RX_POLLING_TIME 0x07
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#define INCA_DMA_TX_HOLD 0x80000000
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#define INCA_DMA_TX_EOP 0x40000000
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#define INCA_DMA_TX_SOP 0x20000000
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#define INCA_DMA_TX_ICPT 0x10000000
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#define INCA_DMA_TX_IEOP 0x08000000
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#define INCA_DMA_TX_HOLD 0x80000000
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#define INCA_DMA_TX_EOP 0x40000000
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#define INCA_DMA_TX_SOP 0x20000000
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#define INCA_DMA_TX_ICPT 0x10000000
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#define INCA_DMA_TX_IEOP 0x08000000
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#define INCA_DMA_RX_C 0x80000000
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#define INCA_DMA_RX_SOP 0x40000000
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#define INCA_DMA_RX_EOP 0x20000000
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#define INCA_DMA_RX_C 0x80000000
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#define INCA_DMA_RX_SOP 0x40000000
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#define INCA_DMA_RX_EOP 0x20000000
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#define INCA_SWITCH_PHY_SPEED_10H 0x1
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#define INCA_SWITCH_PHY_SPEED_10F 0x5
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@ -73,26 +73,26 @@
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#define INCA_SWITCH_PHY_SPEED_100F 0x6
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/************************ Auto MDIX settings ************************/
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
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#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
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#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
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#define WAIT_SIGNAL_RETRIES 100
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#define WAIT_LINK_RETRIES 100
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#define LINK_RETRY_DELAY 300 /* ms */
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#define WAIT_SIGNAL_RETRIES 100
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#define WAIT_LINK_RETRIES 100
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#define LINK_RETRY_DELAY 2000 /* ms */
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/********************************************************************/
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typedef struct
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{
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union {
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struct {
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volatile u32 HOLD :1;
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volatile u32 ICpt :1;
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volatile u32 IEop :1;
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volatile u32 offset :3;
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volatile u32 reserved0 :4;
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volatile u32 NFB :22;
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volatile u32 HOLD :1;
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volatile u32 ICpt :1;
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volatile u32 IEop :1;
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volatile u32 offset :3;
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volatile u32 reserved0 :4;
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volatile u32 NFB :22;
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}field;
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volatile u32 word;
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@ -104,11 +104,11 @@ typedef struct
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union {
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struct {
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 reserved3 :12;
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volatile u32 NBT :17;
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 reserved3 :12;
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volatile u32 NBT :17;
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}field;
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volatile u32 word;
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@ -121,13 +121,13 @@ typedef struct
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{
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union {
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struct {
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volatile u32 HOLD :1;
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volatile u32 Eop :1;
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volatile u32 Sop :1;
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volatile u32 ICpt :1;
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volatile u32 IEop :1;
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volatile u32 reserved0 :5;
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volatile u32 NBA :22;
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volatile u32 HOLD :1;
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volatile u32 Eop :1;
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volatile u32 Sop :1;
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volatile u32 ICpt :1;
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volatile u32 IEop :1;
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volatile u32 reserved0 :5;
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volatile u32 NBA :22;
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}field;
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volatile u32 word;
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@ -137,8 +137,8 @@ typedef struct
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volatile u32 TxDataPtr;
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volatile u32 C :1;
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volatile u32 reserved3 :31;
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volatile u32 C :1;
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volatile u32 reserved3 :31;
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} inca_tx_descriptor_t;
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@ -148,12 +148,11 @@ static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
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static int tx_new, rx_new, tx_hold, rx_hold;
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static int tx_old_hold = -1;
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static int initialized = 0;
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static int initialized = 0;
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static int inca_switch_init(struct eth_device *dev, bd_t * bis);
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static int inca_switch_send(struct eth_device *dev, volatile void *packet,
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int length);
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static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
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static int inca_switch_recv(struct eth_device *dev);
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static void inca_switch_halt(struct eth_device *dev);
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static void inca_init_switch_chip(void);
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@ -265,9 +264,9 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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memset(tx_desc, 0, sizeof(tx_ring[i]));
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tx_desc->params.word = 0;
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tx_desc->params.word = 0;
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tx_desc->params.field.HOLD = 1;
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tx_desc->C = 1;
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tx_desc->C = 1;
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/* Check if it is the last descriptor.
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*/
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@ -296,8 +295,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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/* Writing to the COMMAND REG.
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*/
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DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0,
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INCA_IP_DMA_DMA_RXCCR0_INIT);
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DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
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/* Initialize TxDMA.
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*/
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@ -320,9 +318,9 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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#endif
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/* enable spanning tree forwarding, enable the CPU port */
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/* ST_PT:
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* CPS (CPU port status) 0x3 (forwarding)
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* LPS (LAN port status) 0x3 (forwarding)
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* PPS (PC port status) 0x3 (forwarding)
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* CPS (CPU port status) 0x3 (forwarding)
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* LPS (LAN port status) 0x3 (forwarding)
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* PPS (PC port status) 0x3 (forwarding)
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*/
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SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
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@ -336,11 +334,11 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
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{
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int i;
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int res = -1;
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u32 command;
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u32 regValue;
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inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
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int i;
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int res = -1;
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u32 command;
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u32 regValue;
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inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
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#if 0
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printf("Entered inca_switch_send()\n");
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@ -373,7 +371,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
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KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
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tx_hold = tx_new;
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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if (! initialized) {
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@ -409,7 +407,7 @@ Done:
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static int inca_switch_recv(struct eth_device *dev)
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{
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int length = 0;
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int length = 0;
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inca_rx_descriptor_t * rx_desc;
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#if 0
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@ -450,8 +448,7 @@ static int inca_switch_recv(struct eth_device *dev)
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#if 0
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printf("Received %d bytes\n", length);
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#endif
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NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]),
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length - 4);
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NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
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} else {
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#if 1
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printf("Zero length!!!\n");
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@ -516,13 +513,13 @@ static void inca_init_switch_chip(void)
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#if 1
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/* init MDIO configuration:
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* MDS (Poll speed): 0x01 (4ms)
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* PHY_LAN_ADDR: 0x06
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* PHY_PC_ADDR: 0x05
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* MDS (Poll speed): 0x01 (4ms)
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* PHY_LAN_ADDR: 0x06
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* PHY_PC_ADDR: 0x05
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* UEP (Use External PHY): 0x00 (Internal PHY is used)
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* PS (Port Select): 0x00 (PT/UMM for LAN)
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* PT (PHY Test): 0x00 (no test mode)
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* UMM (Use MDIO Mode): 0x00 (state machine is disabled)
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* PS (Port Select): 0x00 (PT/UMM for LAN)
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* PT (PHY Test): 0x00 (no test mode)
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* UMM (Use MDIO Mode): 0x00 (state machine is disabled)
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*/
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SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
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@ -540,39 +537,39 @@ static void inca_init_switch_chip(void)
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/* MDIO_ACC:
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* RA (Request/Ack) 0x01 (Request)
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* RW (Read/Write) 0x01 (Write)
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* PHY_ADDR 0x05 (PC)
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* REG_ADDR 0x00 (PHY_BCR: basic control register)
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* PHY_DATA 0x8000
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* Reset - software reset
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* LB (loop back) - normal
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* SS (speed select) - 10 Mbit/s
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* RW (Read/Write) 0x01 (Write)
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* PHY_ADDR 0x05 (PC)
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* REG_ADDR 0x00 (PHY_BCR: basic control register)
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* PHY_DATA 0x8000
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* Reset - software reset
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* LB (loop back) - normal
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* SS (speed select) - 10 Mbit/s
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* ANE (auto neg. enable) - enable
|
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* PD (power down) - normal
|
||||
* ISO (isolate) - normal
|
||||
* PD (power down) - normal
|
||||
* ISO (isolate) - normal
|
||||
* RAN (restart auto neg.) - normal
|
||||
* DM (duplex mode) - half duplex
|
||||
* DM (duplex mode) - half duplex
|
||||
* CT (collision test) - enable
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
|
||||
|
||||
/* MDIO_ACC:
|
||||
* RA (Request/Ack) 0x01 (Request)
|
||||
* RW (Read/Write) 0x01 (Write)
|
||||
* PHY_ADDR 0x06 (LAN)
|
||||
* REG_ADDR 0x00 (PHY_BCR: basic control register)
|
||||
* PHY_DATA 0x8000
|
||||
* Reset - software reset
|
||||
* LB (loop back) - normal
|
||||
* SS (speed select) - 10 Mbit/s
|
||||
* RW (Read/Write) 0x01 (Write)
|
||||
* PHY_ADDR 0x06 (LAN)
|
||||
* REG_ADDR 0x00 (PHY_BCR: basic control register)
|
||||
* PHY_DATA 0x8000
|
||||
* Reset - software reset
|
||||
* LB (loop back) - normal
|
||||
* SS (speed select) - 10 Mbit/s
|
||||
* ANE (auto neg. enable) - enable
|
||||
* PD (power down) - normal
|
||||
* ISO (isolate) - normal
|
||||
* PD (power down) - normal
|
||||
* ISO (isolate) - normal
|
||||
* RAN (restart auto neg.) - normal
|
||||
* DM (duplex mode) - half duplex
|
||||
* DM (duplex mode) - half duplex
|
||||
* CT (collision test) - enable
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
|
||||
|
||||
#endif
|
||||
|
||||
@ -723,7 +720,7 @@ static int inca_amdix(void)
|
||||
(0x6 << 21) | /* LAN */
|
||||
(31 << 16)); /* PHY_SCSR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
|
||||
} while (phyReg31 & (1 << 31));
|
||||
|
||||
switch ((phyReg31 >> 2) & 0x7) {
|
||||
@ -755,7 +752,7 @@ static int inca_amdix(void)
|
||||
(0x6 << 21) | /* LAN */
|
||||
(6 << 16)); /* PHY_ANER */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
|
||||
} while (phyReg6 & (1 << 31));
|
||||
|
||||
/* We are Autoneg-able.
|
||||
@ -768,7 +765,7 @@ static int inca_amdix(void)
|
||||
(0x6 << 21) | /* LAN */
|
||||
(4 << 16)); /* PHY_ANAR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
|
||||
} while (phyReg4 & (1 << 31));
|
||||
|
||||
/* We advertise PAUSE capab.
|
||||
@ -781,7 +778,7 @@ static int inca_amdix(void)
|
||||
(0x6 << 21) | /* LAN */
|
||||
(5 << 16)); /* PHY_ANLPAR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
|
||||
} while (phyReg5 & (1 << 31));
|
||||
|
||||
/* Link partner is PAUSE capab.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user