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arm: dts: socfpga: agilex: Add freeze controller node

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The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Dinesh Maniyam 2022-05-31 16:05:56 +08:00 committed by Tien Fong Chee
parent 373c1428a0
commit 7f85330782
1 changed files with 10 additions and 1 deletions
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11
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
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@ -2,7 +2,7 @@
/*
* U-Boot additions
*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_agilex-u-boot.dtsi"
@ -11,6 +11,15 @@
aliases {
spi0 = &qspi;
i2c0 = &i2c1;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@f9000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0xf9000450 0x00000010>;
status = "disabled";
};
};
memory {