random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-14 21:06:01 +01:00
Code Issues Packages Projects Releases Wiki Activity

microblaze: cache: introduce Kconfig options for icache/dcache sizes

Browse Source 
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE

Also, get rid of the hardcoded value in icache_disable().

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
This commit is contained in:
Ovidiu Panait 2022-05-31 21:14:29 +03:00 committed by Michal Simek
parent 73b8ee62a0
commit 84488fc693
5 changed files with 21 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/microblaze/cpu/cache.c
View File

@ -65,8 +65,7 @@ void icache_enable(void)
void icache_disable(void) void icache_disable(void)
{ {
/* we are not generate ICACHE size -> flush whole cache */ __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE);
__invalidate_icache(0, 32768);
MSRCLR(0x20); MSRCLR(0x20);
} }
@ -78,7 +77,7 @@ void dcache_enable(void)
void dcache_disable(void) void dcache_disable(void)
{ {
__flush_dcache(0, XILINX_DCACHE_BYTE_SIZE); __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
MSRCLR(0x80); MSRCLR(0x80);
} }

4
arch/microblaze/cpu/start.S
View File

@ -99,7 +99,7 @@ uboot_sym_start:
/* Flush cache before enable cache */ /* Flush cache before enable cache */
addik r5, r0, 0 addik r5, r0, 0
addik r6, r0, XILINX_DCACHE_BYTE_SIZE addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
brlid r15, flush_cache brlid r15, flush_cache
nop nop
@ -350,7 +350,7 @@ relocate_code:
/* Flush caches to ensure consistency */ /* Flush caches to ensure consistency */
addik r5, r0, 0 addik r5, r0, 0
addik r6, r0, XILINX_DCACHE_BYTE_SIZE addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
brlid r15, flush_cache brlid r15, flush_cache
nop nop

2
arch/microblaze/lib/bootm.c
View File

@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : ""); "(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
flush_cache(0, XILINX_DCACHE_BYTE_SIZE); flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE);
if (!fake) { if (!fake) {
/* /*

16
board/xilinx/microblaze-generic/Kconfig
View File

@ -85,4 +85,20 @@ config SPL_XILINX_MICROBLAZE0_USE_WIC
bool bool
default XILINX_MICROBLAZE0_USE_WIC default XILINX_MICROBLAZE0_USE_WIC
config XILINX_MICROBLAZE0_DCACHE_SIZE
int "Default data cache size"
default 32768
help
This fallback size will be used when no dcache info can be found in
the device tree, or when the data cache is flushed very early in the
boot process, before device tree is available.
config XILINX_MICROBLAZE0_ICACHE_SIZE
int "Default instruction cache size"
default 32768
help
This fallback size will be used when no icache info can be found in
the device tree, or when the instruction cache is flushed very early
in the boot process, before device tree is available.
endif endif

4
include/configs/microblaze-generic.h
View File

@ -26,10 +26,6 @@
# define CONFIG_SYS_MAX_FLASH_SECT 2048 # define CONFIG_SYS_MAX_FLASH_SECT 2048
#endif #endif
#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE 32768
#endif
/* size of console buffer */ /* size of console buffer */
#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_CBSIZE 512
/* max number of command args */ /* max number of command args */