random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-11-27 06:14:41 +00:00
Code Issues Packages Projects Releases Wiki Activity

usb: dwc3-generic: implement Qualcomm wrapper

Browse Source 
The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented
the missing initialisation for host and gadget mode.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-1-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This commit is contained in:
Caleb Connolly 2024-03-20 14:30:47 +00:00 committed by Mattijs Korpershoek
parent e50cb36cb5
commit 850b307789
1 changed files with 80 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

81
drivers/usb/dwc3/dwc3-generic.c
View File

@ -425,6 +425,77 @@ struct dwc3_glue_ops ti_ops = {
.glue_configure = dwc3_ti_glue_configure,
};
/* USB QSCRATCH Hardware registers */
#define QSCRATCH_GENERAL_CFG 0x08
#define PIPE_UTMI_CLK_SEL BIT(0)
#define PIPE3_PHYSTATUS_SW BIT(3)
#define PIPE_UTMI_CLK_DIS BIT(8)
#define QSCRATCH_HS_PHY_CTRL 0x10
#define UTMI_OTG_VBUS_VALID BIT(20)
#define SW_SESSVLD_SEL BIT(28)
#define QSCRATCH_SS_PHY_CTRL 0x30
#define LANE0_PWR_PRESENT BIT(24)
#define PWR_EVNT_IRQ_STAT_REG 0x58
#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
#define SDM845_QSCRATCH_SIZE 0x400
#define SDM845_DWC3_CORE_SIZE 0xcd00
static void dwc3_qcom_vbus_override_enable(void __iomem *qscratch_base, bool enable)
{
if (enable) {
setbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
LANE0_PWR_PRESENT);
setbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
} else {
clrbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
LANE0_PWR_PRESENT);
clrbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
}
}
/* For controllers running without superspeed PHYs */
static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
{
/* Configure dwc3 to use UTMI clock as PIPE clock not present */
setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
PIPE_UTMI_CLK_DIS);
setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
PIPE_UTMI_CLK_DIS);
}
static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
struct dwc3_glue_data *glue = dev_get_plat(dev);
void __iomem *qscratch_base = map_physmem(glue->regs, 0x400, MAP_NOCACHE);
if (IS_ERR_OR_NULL(qscratch_base)) {
log_err("%s: Invalid qscratch base address\n", dev->name);
return;
}
if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
dwc3_qcom_select_utmi_clk(qscratch_base);
if (mode != USB_DR_MODE_HOST)
dwc3_qcom_vbus_override_enable(qscratch_base, true);
}
struct dwc3_glue_ops qcom_ops = {
.glue_configure = dwc3_qcom_glue_configure,
};
static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
{
*node = dev_ofnode(dev);
@ -512,6 +583,14 @@ static int dwc3_glue_reset_init(struct udevice *dev,
else if (ret)
return ret;
if (device_is_compatible(dev, "qcom,dwc3")) {
reset_assert_bulk(&glue->resets);
/* We should wait at least 6 sleep clock cycles, that's
* (6 / 32764) * 1000000 ~= 200us. But some platforms
* have slower sleep clocks so we'll play it safe.
*/
udelay(500);
}
ret = reset_deassert_bulk(&glue->resets);
if (ret) {
reset_release_bulk(&glue->resets);
@ -629,7 +708,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3" },
{ .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },