mirror of
https://github.com/smaeul/u-boot.git
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Merge tag 'fsl-qoriq-2022-7-29' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
mpc85xx: support for generating QorIQ pre-PBL eSDHC boot sector p1_p2_rdb_pc: Remove I-flag from second L2 SRAM mapping p1_p2_rdb_pc: Fix parsing inverted bits from boot input data p1_p2_rdb_pc: Simplify SPL offset macros
This commit is contained in:
commit
85eb5ac6ef
@ -12,6 +12,59 @@ config CMD_ERRATA
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This enables the 'errata' command which displays a list of errata
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This enables the 'errata' command which displays a list of errata
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work-arounds which are enabled for the current board.
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work-arounds which are enabled for the current board.
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config FSL_PREPBL_ESDHC_BOOT_SECTOR
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bool "Generate QorIQ pre-PBL eSDHC boot sector"
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depends on MPC85xx
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depends on SYS_EXTRA_OPTIONS = SDCARD
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help
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With this option final image would have prepended QorIQ pre-PBL eSDHC
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boot sector suitable for SD card images. This boot sector instruct
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BootROM to configure L2 SRAM and eSDHC then load image from SD card
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into L2 SRAM and finally jump to image entry point.
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This is alternative to Freescale boot_format tool, but works only for
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SD card images and only for L2 SRAM booting. U-Boot images generated
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with this option should not passed to boot_format tool.
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For other configuration like booting from eSPI or configuring SDRAM
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please use Freescale boot_format tool without this option. See file
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doc/README.mpc85xx-sd-spi-boot
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config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
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int "QorIQ pre-PBL eSDHC boot sector start offset"
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depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
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range 0 23
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default 0
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help
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QorIQ pre-PBL eSDHC boot sector may be located on one of the first
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24 SD card sectors. Select SD card sector on which final U-Boot
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image (with this boot sector) would be installed.
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By default first SD card sector (0) is used. But this may be changed
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to allow installing U-Boot image on some partition (with fixed start
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sector).
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Please note that any sector on SD card prior this boot sector must
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not contain ASCII "BOOT" bytes at sector offset 0x40.
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config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
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int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
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depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
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default 1
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range 1 8388607
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help
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Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
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sector on which would be stored raw U-Boot image.
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By default is it second sector (1) which is the first available free
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sector (on the first sector is stored boot sector). It can be any
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sector number which offset in bytes can be expressed by 32-bit number.
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In case this final U-Boot image (with this boot sector) is put on
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the FAT32 partition into reserved boot area, this data sector needs
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to be at least 2 (third sector) because FAT32 use second sector for
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its data.
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choice
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choice
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prompt "Target select"
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prompt "Target select"
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optional
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optional
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@ -57,6 +57,100 @@
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GOT_ENTRY(__bss_start)
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GOT_ENTRY(__bss_start)
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END_GOT
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END_GOT
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#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* Maximal size of the image */
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#ifdef CONFIG_SPL_BUILD
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#define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512))
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#else
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#define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE
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#endif
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#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512
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#error "CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA"
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#endif
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#if MAX_IMAGE_SIZE > CONFIG_SYS_L2_SIZE
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#error "Image is too big"
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#endif
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#define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
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#define ALIGN(x, a) (DIV_ROUND_UP(x, a) * (a))
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/* Definitions from C header file asm/immap_85xx.h */
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#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
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#define MPC85xx_L2CTL 0x000
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#define MPC85xx_L2CTL_L2E 0x80000000
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#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
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#define MPC85xx_L2SRBAR0 0x100
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#define MPC85xx_L2ERRDIS 0xe44
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#define MPC85xx_L2ERRDIS_MBECC 0x00000008
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#define MPC85xx_L2ERRDIS_SBECC 0x00000004
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/* Definitions from C header file fsl_esdhc.h */
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#define ESDHCCTL 0x0002e40c
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#define ESDHCCTL_SNOOP 0x00000040
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/*
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* QorIQ pre-PBL eSDHC boot sector:
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* Instruct BootROM to configure L2 SRAM and eSDHC then load image
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* from SD card into L2 SRAM and finally jump to image entry point.
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*/
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.section .bootsect, "a"
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.globl bootsect
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bootsect:
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.org 0x40 /* BOOT signature */
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.ascii "BOOT"
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.org 0x48 /* Number of bytes to be copied, must be multiple of block size (512) */
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.long ALIGN(MAX_IMAGE_SIZE, 512)
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.org 0x50 /* Source address from the beginning of boot sector in byte address format, must be multiple of block size (512) */
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.long (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_START + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA) * 512
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.org 0x58 /* Target address in the system's local memory address space */
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.long CONFIG_SYS_MONITOR_BASE
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.org 0x60 /* Execution starting address */
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.long _start
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.org 0x68 /* Number of configuration data pairs */
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.long DIV_ROUND_UP(.Lconf_pair_end - .Lconf_pair_start, 8)
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.org 0x80 /* Start of configuration */
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.Lconf_pair_start:
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.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
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.long CONFIG_SYS_INIT_L2_ADDR
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.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
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.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
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.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
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.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
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.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
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.long ESDHCCTL_SNOOP
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.long 0x40000001 /* Command: Delay in 8 CCB clocks */
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.long 256
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.long 0x80000001 /* End of configuration */
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.Lconf_pair_end:
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.org 0x1b8 /* Reserved for MBR/DBR */
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.org 0x200 /* End of boot sector */
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#endif
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#endif
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/*
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/*
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* e500 Startup -- after reset only the last 4KB of the effective
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* e500 Startup -- after reset only the last 4KB of the effective
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* address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
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* address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
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@ -12,6 +12,14 @@ OUTPUT_ARCH(powerpc)
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SECTIONS
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SECTIONS
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{
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{
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/* Optional boot sector */
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#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR)
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.bootsect IMAGE_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {
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KEEP(*(.bootsect))
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. = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;
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}
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#endif
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. = IMAGE_TEXT_BASE;
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. = IMAGE_TEXT_BASE;
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.text : {
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.text : {
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/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
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/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
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@ -16,6 +16,14 @@ ENTRY(_start)
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SECTIONS
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SECTIONS
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{
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{
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/* Optional boot sector */
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#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) && !defined(CONFIG_SPL)
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.bootsect CONFIG_SYS_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {
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KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootsect))
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. = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;
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}
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#endif
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/* Read-only sections, merged into text segment: */
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/* Read-only sections, merged into text segment: */
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.text :
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.text :
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{
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{
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@ -182,7 +182,7 @@ int checkboard(void)
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{
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u8 in, out, io_config, val;
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u8 in, out, invert, io_config, val;
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int bus_num = CONFIG_SYS_SPD_BUS_NUM;
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int bus_num = CONFIG_SYS_SPD_BUS_NUM;
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/* FIXME: This should just use the model from the device tree or similar */
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/* FIXME: This should just use the model from the device tree or similar */
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@ -210,6 +210,7 @@ int checkboard(void)
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if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
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if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
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dm_i2c_read(dev, 1, &out, 1) < 0 ||
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dm_i2c_read(dev, 1, &out, 1) < 0 ||
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dm_i2c_read(dev, 2, &invert, 1) < 0 ||
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dm_i2c_read(dev, 3, &io_config, 1) < 0) {
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dm_i2c_read(dev, 3, &io_config, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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return 0; /* Don't want to hang() on this error */
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@ -219,13 +220,14 @@ int checkboard(void)
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if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
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if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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return 0; /* Don't want to hang() on this error */
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}
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}
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#endif
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#endif
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val = (in & io_config) | (out & (~io_config));
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val = ((in ^ invert) & io_config) | (out & (~io_config));
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puts("rom_loc: ");
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puts("rom_loc: ");
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if (0) {
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if (0) {
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@ -90,14 +90,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
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#endif /* RAMBOOT/SPL */
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#endif /* RAMBOOT/SPL */
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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/* *I*G - L2SRAM */
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/* ***G - L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 11, BOOKE_PAGESZ_256K, 1),
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0, 11, BOOKE_PAGESZ_256K, 1),
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#if CONFIG_SYS_L2_SIZE >= (256 << 10)
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#if CONFIG_SYS_L2_SIZE >= (256 << 10)
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 12, BOOKE_PAGESZ_256K, 1)
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0, 12, BOOKE_PAGESZ_256K, 1)
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#endif
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#endif
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#endif
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#endif
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@ -78,14 +78,14 @@
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#ifdef CONFIG_SDCARD
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#ifdef CONFIG_SDCARD
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#elif defined(CONFIG_SPIFLASH)
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#elif defined(CONFIG_SPIFLASH)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#elif defined(CONFIG_MTD_RAW_NAND)
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#elif defined(CONFIG_MTD_RAW_NAND)
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#ifdef CONFIG_TPL_BUILD
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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