mirror of
https://github.com/smaeul/u-boot.git
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dts: qcs404-evb: replace with upstream DT
Drop the U-Boot specific DTS in favour of upstream. We'll only include the -4000 variant as that is what U-Boot already supported. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly
parent
4745c4d76c
commit
890207c651
@ -628,7 +628,7 @@ dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
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apq8096-db820c.dtb \
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sdm845-db845c.dtb \
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sdm845-samsung-starqltechn.dtb \
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qcs404-evb.dtb
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qcs404-evb-4000.dtb
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dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
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149
arch/arm/dts/pms405.dtsi
Normal file
149
arch/arm/dts/pms405.dtsi
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@ -0,0 +1,149 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, Linaro Limited
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*/
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#include <dt-bindings/spmi/spmi.h>
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#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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thermal-zones {
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pms405-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&pms405_temp>;
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trips {
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pms405_alert0: pms405-alert0 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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pms405_crit: pms405-crit {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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};
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&spmi_bus {
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pms405_0: pms405@0 {
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compatible = "qcom,pms405", "qcom,spmi-pmic";
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reg = <0x0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pms405_gpios: gpio@c000 {
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compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
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reg = <0xc000>;
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gpio-controller;
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gpio-ranges = <&pms405_gpios 0 0 12>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pon@800 {
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compatible = "qcom,pms405-pon";
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reg = <0x0800>;
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mode-bootloader = <0x2>;
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mode-recovery = <0x1>;
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pwrkey {
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compatible = "qcom,pm8941-pwrkey";
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interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
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debounce = <15625>;
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bias-pull-up;
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linux,code = <KEY_POWER>;
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};
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};
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pms405_temp: temp-alarm@2400 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0x2400>;
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interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
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io-channels = <&pms405_adc ADC5_DIE_TEMP>;
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io-channel-names = "thermal";
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#thermal-sensor-cells = <0>;
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};
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pms405_adc: adc@3100 {
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compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
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reg = <0x3100>;
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interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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channel@0 {
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reg = <ADC5_REF_GND>;
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qcom,pre-scaling = <1 1>;
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label = "ref_gnd";
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};
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channel@1 {
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reg = <ADC5_1P25VREF>;
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qcom,pre-scaling = <1 1>;
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label = "vref_1p25";
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};
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channel@131 {
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reg = <ADC5_VPH_PWR>;
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qcom,pre-scaling = <1 3>;
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label = "vph_pwr";
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};
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channel@6 {
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reg = <ADC5_DIE_TEMP>;
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qcom,pre-scaling = <1 1>;
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label = "die_temp";
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};
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channel@77 {
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reg = <ADC5_AMUX_THM1_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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label = "pa_therm1";
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};
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channel@79 {
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reg = <ADC5_AMUX_THM3_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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label = "pa_therm3";
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};
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channel@76 {
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reg = <ADC5_XO_THERM_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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label = "xo_therm";
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};
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};
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rtc@6000 {
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compatible = "qcom,pm8941-rtc";
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reg = <0x6000>, <0x6100>;
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reg-names = "rtc", "alarm";
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interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
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};
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};
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pms405_1: pms405@1 {
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compatible = "qcom,pms405", "qcom,spmi-pmic";
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reg = <0x1 SPMI_USID>;
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pms405_spmi_regulators: regulators {
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compatible = "qcom,pms405-regulators";
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};
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};
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};
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48
arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
Normal file
48
arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
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@ -0,0 +1,48 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/gpio/gpio.h>
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/delete-node/ &usb3_vbus_reg;
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/delete-node/ &usb_vbus_boost_pin;
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/ {
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/* U-Boot uses different bindings for GPIO regulators, this
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* one is required for USB
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*/
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usb3_vbus_reg: usb3_vbus_reg {
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compatible = "regulator-gpio";
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regulator-name = "usb3_vbus_reg";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-gpios = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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states = <0 0>, <5000000 1>;
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};
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};
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&blsp1_uart2 {
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/* This defines the bit clock divider which defines the baud rate.
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* 0xFF is a divider of 16 for both the RX and TX lines. The QCS404
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* clock driver in U-Boot hardcodes a 1843200Hz frequency for the
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* UART core clock, and 1843200 / 16 = 115200.
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*/
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bit-rate = <0xFF>;
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};
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&gcc {
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/* The clock framework in U-Boot "sort of" has the idea of linking an
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* individual clock to a device via uclass_priv. However the qcom clock
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* driver instead associates many clocks with a single device. This is
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* usually fine but it seems that assigned-clocks wreak havoc on this
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* and we wind up having a reference to the XO clock which is associated
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* with the qcom_clk device...
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* For now we'll just remove these properties, no other board has these.
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*/
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/delete-property/ assigned-clock-rates;
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/delete-property/ assigned-clocks;
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};
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&usb3_dwc3 {
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/* Make sure the VBUS supply is switched on */
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vbus-supply = <&usb3_vbus_reg>;
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};
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96
arch/arm/dts/qcs404-evb-4000.dts
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96
arch/arm/dts/qcs404-evb-4000.dts
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@ -0,0 +1,96 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, Linaro Limited
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "qcs404-evb.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
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compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
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"qcom,qcs404";
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};
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ðernet {
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status = "okay";
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snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 10000>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_defaults>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy1: phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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device_type = "ethernet-phy";
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reg = <0x4>;
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};
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};
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};
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&tlmm {
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ethernet_defaults: ethernet-defaults-state {
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int-pins {
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pins = "gpio61";
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function = "rgmii_int";
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bias-disable;
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drive-strength = <2>;
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};
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mdc-pins {
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pins = "gpio76";
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function = "rgmii_mdc";
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bias-pull-up;
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};
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mdio-pins {
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pins = "gpio75";
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function = "rgmii_mdio";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio67", "gpio66", "gpio65", "gpio64";
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function = "rgmii_tx";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-pins {
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pins = "gpio73", "gpio72", "gpio71", "gpio70";
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function = "rgmii_rx";
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bias-disable;
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drive-strength = <2>;
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};
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tx-ctl-pins {
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pins = "gpio68";
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function = "rgmii_ctl";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-ctl-pins {
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pins = "gpio74";
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function = "rgmii_ctl";
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bias-disable;
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drive-strength = <2>;
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};
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tx-ck-pins {
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pins = "gpio63";
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function = "rgmii_ck";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-ck-pins {
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pins = "gpio69";
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function = "rgmii_ck";
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bias-disable;
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drive-strength = <2>;
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};
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};
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};
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@ -1,30 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot addition to handle QCS404 EVB pre-relocation devices
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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/ {
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soc {
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bootph-all;
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pinctrl_north@1300000 {
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bootph-all;
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};
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clock-controller@1800000 {
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bootph-all;
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};
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serial@78b1000 {
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bootph-all;
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};
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};
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};
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&pms405_gpios {
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usb_vbus_boost_pin {
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gpios = <&pms405_gpios 2 0>;
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};
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};
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@ -1,390 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm QCS404 based evaluation board device tree source
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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/ {
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model = "Qualcomm Technologies, Inc. QCS404 EVB";
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compatible = "qcom,qcs404-evb", "qcom,qcs404";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &debug_uart;
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i2c0 = &blsp1_i2c0;
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i2c1 = &blsp1_i2c1;
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i2c2 = &blsp1_i2c2;
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i2c3 = &blsp1_i2c3;
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i2c4 = &blsp1_i2c4;
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};
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memory {
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device_type = "memory";
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reg = <0 0x80000000 0 0x40000000>;
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};
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soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0x0 0x0 0x0 0xffffffff>;
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compatible = "simple-bus";
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soc_gpios: pinctrl_north@1300000 {
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compatible = "qcom,qcs404-pinctrl";
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reg = <0x1300000 0x200000>;
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gpio-controller;
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gpio-count = <120>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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blsp1_uart2: uart {
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pins = "GPIO_17", "GPIO_18";
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function = "blsp_uart2";
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};
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blsp1_i2c0_default: blsp1-i2c0-default {
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pins = "GPIO_32", "GPIO_33";
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function = "blsp_i2c0";
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};
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blsp1_i2c1_default: blsp1-i2c1-default {
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pins = "GPIO_24", "GPIO_25";
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function = "blsp_i2c1";
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};
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blsp1_i2c2_default: blsp1-i2c2-default {
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sda {
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pins = "GPIO_19";
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function = "blsp_i2c_sda_a2";
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};
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scl {
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pins = "GPIO_20";
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function = "blsp_i2c_scl_a2";
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};
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};
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blsp1_i2c3_default: blsp1-i2c3-default {
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pins = "GPIO_84", "GPIO_85";
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function = "blsp_i2c3";
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};
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blsp1_i2c4_default: blsp1-i2c4-default {
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pins = "GPIO_117", "GPIO_118";
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function = "blsp_i2c4";
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};
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ethernet_defaults: ethernet-defaults {
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int {
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pins = "GPIO_61";
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function = "rgmii_int";
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bias-disable;
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drive-strength = <2>;
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};
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mdc {
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pins = "GPIO_76";
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function = "rgmii_mdc";
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bias-pull-up;
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};
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mdio {
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pins = "GPIO_75";
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function = "rgmii_mdio";
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bias-pull-up;
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};
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tx {
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pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64";
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function = "rgmii_tx";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx {
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pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70";
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function = "rgmii_rx";
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bias-disable;
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drive-strength = <2>;
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};
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tx-ctl {
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pins = "GPIO_68";
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function = "rgmii_ctl";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-ctl {
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pins = "GPIO_74";
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function = "rgmii_ctl";
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bias-disable;
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drive-strength = <2>;
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};
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tx-ck {
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pins = "GPIO_63";
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function = "rgmii_ck";
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bias-pull-up;
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drive-strength = <16>;
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};
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rx-ck {
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pins = "GPIO_69";
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function = "rgmii_ck";
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bias-disable;
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drive-strength = <2>;
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};
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};
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};
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blsp1_i2c0: i2c@78b5000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x078b5000 0x600>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c0_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp1_i2c1: i2c@78b6000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b6000 0x600>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c1_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp1_i2c2: i2c@78b7000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b7000 0x600>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c2_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp1_i2c3: i2c@78b8000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b8000 0x600>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c3_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp1_i2c4: i2c@78b9000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b9000 0x600>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c4_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-qcs404";
|
||||
reg = <0x1800000 0x80000>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
debug_uart: serial@78b1000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4";
|
||||
reg = <0x78b1000 0x200>;
|
||||
clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
bit-rate = <0xFF>;
|
||||
pinctrl-names = "uart";
|
||||
pinctrl-0 = <&blsp1_uart2>;
|
||||
};
|
||||
|
||||
sdhci@7804000 {
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
reg = <0x7804000 0x1000 0x7805000 0x1000>;
|
||||
clock = <&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&gcc GCC_SDCC1_AHB_CLK>;
|
||||
bus-width = <0x8>;
|
||||
index = <0x0>;
|
||||
non-removable;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
};
|
||||
|
||||
usb3_phy: phy@78000 {
|
||||
compatible = "qcom,usb-ss-28nm-phy";
|
||||
#phy-cells = <0>;
|
||||
reg = <0x78000 0x400>;
|
||||
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
|
||||
<&gcc GCC_USB3_PHY_PIPE_CLK>;
|
||||
clock-names = "ahb", "pipe";
|
||||
resets = <&gcc GCC_USB3_PHY_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_BCR>;
|
||||
reset-names = "com", "phy";
|
||||
};
|
||||
|
||||
usb2_phy_prim: phy@7a000 {
|
||||
compatible = "qcom,usb-hs-28nm-femtophy";
|
||||
#phy-cells = <0>;
|
||||
reg = <0x7a000 0x200>;
|
||||
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
|
||||
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
|
||||
clock-names = "ahb", "sleep";
|
||||
resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
|
||||
<&gcc GCC_USB2A_PHY_BCR>;
|
||||
reset-names = "phy", "por";
|
||||
};
|
||||
|
||||
usb2_phy_sec: phy@7c000 {
|
||||
compatible = "qcom,usb-hs-28nm-femtophy";
|
||||
#phy-cells = <0>;
|
||||
reg = <0x7c000 0x200>;
|
||||
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
|
||||
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
|
||||
clock-names = "ahb", "sleep";
|
||||
resets = <&gcc GCC_QUSB2_PHY_BCR>,
|
||||
<&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
|
||||
reset-names = "phy", "por";
|
||||
};
|
||||
|
||||
usb3: usb@7678800 {
|
||||
compatible = "qcom,dwc3";
|
||||
reg = <0x7678800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clocks = <&gcc GCC_USB30_MASTER_CLK>,
|
||||
<&gcc GCC_SYS_NOC_USB3_CLK>,
|
||||
<&gcc GCC_USB30_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
|
||||
clock-names = "core", "iface", "sleep", "mock_utmi";
|
||||
|
||||
dwc3@7580000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x7580000 0xcd00>;
|
||||
phys = <&usb2_phy_prim>, <&usb3_phy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
dr_mode = "host";
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x10>;
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
};
|
||||
|
||||
usb2: usb@79b8800 {
|
||||
compatible = "qcom,dwc3";
|
||||
reg = <0x79b8800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
|
||||
<&gcc GCC_PCNOC_USB2_CLK>,
|
||||
<&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
|
||||
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
|
||||
clock-names = "core", "iface", "sleep", "mock_utmi";
|
||||
|
||||
dwc3@78c0000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x78c0000 0xcc00>;
|
||||
phys = <&usb2_phy_sec>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "peripheral";
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x10>;
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet: ethernet@7a80000 {
|
||||
compatible = "qcom,qcs404-ethqos";
|
||||
reg = <0x07a80000 0x10000>,
|
||||
<0x07a96000 0x100>;
|
||||
reg-names = "stmmaceth", "rgmii";
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
|
||||
clocks = <&gcc GCC_ETH_AXI_CLK>,
|
||||
<&gcc GCC_ETH_SLAVE_AHB_CLK>,
|
||||
<&gcc GCC_ETH_PTP_CLK>,
|
||||
<&gcc GCC_ETH_RGMII_CLK>;
|
||||
|
||||
resets = <&gcc GCC_EMAC_BCR>;
|
||||
reset-names = "emac";
|
||||
|
||||
snps,tso;
|
||||
rx-fifo-depth = <4096>;
|
||||
tx-fifo-depth = <4096>;
|
||||
|
||||
snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 10000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_defaults>;
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
max-speed = <1000>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy1: phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spmi@200f000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0x200f000 0x001000>,
|
||||
<0x2400000 0x800000>,
|
||||
<0x2c00000 0x800000>;
|
||||
reg-names = "core", "chnls", "obsrvr";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
pms405_0: pms405@0 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <0x0 0x1>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
pms405_gpios: pms405_gpios@c000 {
|
||||
compatible = "qcom,pms405-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pms405_gpios 0 0 12>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "qcs404-evb-uboot.dtsi"
|
||||
389
arch/arm/dts/qcs404-evb.dtsi
Normal file
389
arch/arm/dts/qcs404-evb.dtsi
Normal file
@ -0,0 +1,389 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018, Linaro Limited
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "qcs404.dtsi"
|
||||
#include "pms405.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &blsp1_uart2;
|
||||
serial1 = &blsp1_uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_ch0_3p3:
|
||||
vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "eSMPS3_3P3";
|
||||
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usb3_vbus_reg: regulator-usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VBUS_BOOST_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_vbus_boost_pin>;
|
||||
vin-supply = <&vph_pwr>;
|
||||
enable-active-high;
|
||||
|
||||
/* TODO: Drop this when introducing role switching */
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart3 {
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn3990-bt";
|
||||
vddio-supply = <&vreg_l6_1p8>;
|
||||
vddxo-supply = <&vreg_l5_1p8>;
|
||||
vddrf-supply = <&vreg_l1_1p3>;
|
||||
vddch0-supply = <&vdd_ch0_3p3>;
|
||||
|
||||
local-bd-address = [ 02 00 00 00 5a ad ];
|
||||
|
||||
max-speed = <3200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_dma {
|
||||
qcom,controlled-remotely;
|
||||
};
|
||||
|
||||
&blsp2_dma {
|
||||
qcom,controlled-remotely;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_BIMC_CDSP_CLK>,
|
||||
<GCC_CDSP_CFG_AHB_CLK>,
|
||||
<GCC_CDSP_BIMC_CLK_SRC>,
|
||||
<GCC_CDSP_TBU_CLK>,
|
||||
<141>, /* GCC_WCSS_Q6_AHB_CLK */
|
||||
<142>; /* GCC_WCSS_Q6_AXIM_CLK */
|
||||
};
|
||||
|
||||
&pms405_spmi_regulators {
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
|
||||
pms405_s3: s3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vdd_apc";
|
||||
regulator-initial-mode = <1>;
|
||||
regulator-min-microvolt = <1048000>;
|
||||
regulator-max-microvolt = <1384000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
|
||||
perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&perst_state>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-vp-supply = <&vreg_l3_1p05>;
|
||||
vdda-vph-supply = <&vreg_l5_1p8>;
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_wcss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
regulators {
|
||||
compatible = "qcom,rpm-pms405-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
vdd_s2-supply = <&vph_pwr>;
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
vdd_s4-supply = <&vph_pwr>;
|
||||
vdd_s5-supply = <&vph_pwr>;
|
||||
vdd_l1_l2-supply = <&vreg_s5_1p35>;
|
||||
vdd_l3_l8-supply = <&vreg_s5_1p35>;
|
||||
vdd_l4-supply = <&vreg_s5_1p35>;
|
||||
vdd_l5_l6-supply = <&vreg_s4_1p8>;
|
||||
vdd_l7-supply = <&vph_pwr>;
|
||||
vdd_l9-supply = <&vreg_s5_1p35>;
|
||||
vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s4_1p8: s4 {
|
||||
regulator-min-microvolt = <1728000>;
|
||||
regulator-max-microvolt = <1920000>;
|
||||
};
|
||||
|
||||
vreg_s5_1p35: s5 {
|
||||
regulator-min-microvolt = <1352000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
vreg_l1_1p3: l1 {
|
||||
regulator-min-microvolt = <1240000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
vreg_l2_1p275: l2 {
|
||||
regulator-min-microvolt = <1048000>;
|
||||
regulator-max-microvolt = <1280000>;
|
||||
};
|
||||
|
||||
vreg_l3_1p05: l3 {
|
||||
regulator-min-microvolt = <1048000>;
|
||||
regulator-max-microvolt = <1160000>;
|
||||
};
|
||||
|
||||
vreg_l4_1p2: l4 {
|
||||
regulator-min-microvolt = <1144000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
};
|
||||
|
||||
vreg_l5_1p8: l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vreg_l6_1p8: l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l7_1p8: l7 {
|
||||
regulator-min-microvolt = <1616000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vreg_l8_1p2: l8 {
|
||||
regulator-min-microvolt = <1136000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
vreg_l10_3p3: l10 {
|
||||
regulator-min-microvolt = <2936000>;
|
||||
regulator-max-microvolt = <3088000>;
|
||||
};
|
||||
|
||||
vreg_l11_sdc2: l11 {
|
||||
regulator-min-microvolt = <2696000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
};
|
||||
|
||||
vreg_l12_3p3: l12 {
|
||||
regulator-min-microvolt = <3050000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vreg_l13_3p3: l13 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdcc1 {
|
||||
status = "okay";
|
||||
|
||||
supports-cqe;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_on>;
|
||||
pinctrl-1 = <&sdc1_off>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
perst_state: perst-state {
|
||||
pins = "gpio43";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
sdc1_on: sdc1-on-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
rclk-pins {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_off: sdc1-off-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
rclk-pins {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
usb3_id_pin: usb3-id-state {
|
||||
pins = "gpio116";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&pms405_gpios {
|
||||
usb_vbus_boost_pin: usb-vbus-boost-state {
|
||||
pinconf {
|
||||
pins = "gpio3";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
output-low;
|
||||
power-source = <1>;
|
||||
};
|
||||
};
|
||||
usb3_vbus_pin: usb3-vbus-state {
|
||||
pinconf {
|
||||
pins = "gpio12";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
power-source = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy_sec {
|
||||
vdd-supply = <&vreg_l4_1p2>;
|
||||
vdda1p8-supply = <&vreg_l5_1p8>;
|
||||
vdda3p3-supply = <&vreg_l12_3p3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
|
||||
};
|
||||
|
||||
&usb3_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb2_phy_prim {
|
||||
vdd-supply = <&vreg_l4_1p2>;
|
||||
vdda1p8-supply = <&vreg_l5_1p8>;
|
||||
vdda3p3-supply = <&vreg_l12_3p3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy {
|
||||
vdd-supply = <&vreg_l3_1p05>;
|
||||
vdda1p8-supply = <&vreg_l5_1p8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
|
||||
vdd-1.8-xo-supply = <&vreg_l5_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
|
||||
};
|
||||
|
||||
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
|
||||
|
||||
&blsp1_uart2_default {
|
||||
rx-pins {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx-pins {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart3_default {
|
||||
cts-pins {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rts-tx-pins {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
1829
arch/arm/dts/qcs404.dtsi
Normal file
1829
arch/arm/dts/qcs404.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user