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	fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig
This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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							@ -1330,10 +1330,6 @@ The following options need to be configured:
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		Enables support for FPGA family.
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							Enables support for FPGA family.
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		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
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							(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
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		CONFIG_SYS_FPGA_PROG_FEEDBACK
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		Enable printing of hash marks during FPGA configuration.
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		CONFIG_SYS_FPGA_CHECK_BUSY
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							CONFIG_SYS_FPGA_CHECK_BUSY
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		Enable checks on FPGA configuration interface busy
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							Enable checks on FPGA configuration interface busy
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@ -33,6 +33,7 @@ CONFIG_FPGA_ALTERA=y
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CONFIG_FPGA_CYCLON2=y
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					CONFIG_FPGA_CYCLON2=y
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CONFIG_FPGA_XILINX=y
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					CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_SPARTAN3=y
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					CONFIG_FPGA_SPARTAN3=y
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					CONFIG_SYS_FPGA_PROG_FEEDBACK=y
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CONFIG_SYS_I2C_LEGACY=y
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					CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_FSL=y
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					CONFIG_SYS_I2C_FSL=y
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CONFIG_SYS_FSL_I2C_OFFSET=0x58000
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					CONFIG_SYS_FSL_I2C_OFFSET=0x58000
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@ -97,4 +97,11 @@ config SYS_FPGA_CHECK_CTRLC
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	help
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						help
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	  User can interrupt FPGA configuration by pressing CTRL+C.
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						  User can interrupt FPGA configuration by pressing CTRL+C.
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					config SYS_FPGA_PROG_FEEDBACK
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						bool "Progress output during FPGA configuration"
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						depends on FPGA
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						default y if FPGA_VIRTEX2
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						help
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						  Enable printing of hash marks during FPGA configuration.
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endmenu
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					endmenu
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@ -15,7 +15,6 @@
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#endif
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					#endif
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#undef CONFIG_SYS_FPGA_CHECK_BUSY
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					#undef CONFIG_SYS_FPGA_CHECK_BUSY
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#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
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/* Note: The assumption is that we cannot possibly run fast enough to
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					/* Note: The assumption is that we cannot possibly run fast enough to
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 * overrun the device (the Slave Parallel mode can free run at 50MHz).
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					 * overrun the device (the Slave Parallel mode can free run at 50MHz).
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@ -41,10 +41,6 @@
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#define CONFIG_FPGA_DELAY()
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					#define CONFIG_FPGA_DELAY()
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#endif
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					#endif
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#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK
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#endif
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/*
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					/*
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 * Check for errors during configuration by default
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					 * Check for errors during configuration by default
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 */
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					 */
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@ -131,7 +131,6 @@
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 * it needs non-blocking CFI routines.
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					 * it needs non-blocking CFI routines.
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 */
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					 */
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_SYS_FPGA_WAIT		1000
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					#define CONFIG_SYS_FPGA_WAIT		1000
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/* End of user parameters to be customized */
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					/* End of user parameters to be customized */
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@ -743,7 +743,6 @@ CONFIG_SYS_FPGA_FTIM0
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CONFIG_SYS_FPGA_FTIM1
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					CONFIG_SYS_FPGA_FTIM1
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CONFIG_SYS_FPGA_FTIM2
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					CONFIG_SYS_FPGA_FTIM2
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CONFIG_SYS_FPGA_FTIM3
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					CONFIG_SYS_FPGA_FTIM3
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CONFIG_SYS_FPGA_PROG_FEEDBACK
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CONFIG_SYS_FPGA_SIZE
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					CONFIG_SYS_FPGA_SIZE
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CONFIG_SYS_FPGA_WAIT
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					CONFIG_SYS_FPGA_WAIT
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CONFIG_SYS_FSL_BMAN_ADDR
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					CONFIG_SYS_FSL_BMAN_ADDR
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