fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig

This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Alexander Dahl 2022-07-21 15:31:22 +02:00 committed by Michal Simek
parent e8ffc1dfcb
commit 8c09cb6f4d
7 changed files with 8 additions and 11 deletions

4
README
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@ -1330,10 +1330,6 @@ The following options need to be configured:
Enables support for FPGA family. Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
CONFIG_SYS_FPGA_CHECK_BUSY CONFIG_SYS_FPGA_CHECK_BUSY
Enable checks on FPGA configuration interface busy Enable checks on FPGA configuration interface busy

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@ -33,6 +33,7 @@ CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_FPGA_PROG_FEEDBACK=y
CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x58000 CONFIG_SYS_FSL_I2C_OFFSET=0x58000

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@ -97,4 +97,11 @@ config SYS_FPGA_CHECK_CTRLC
help help
User can interrupt FPGA configuration by pressing CTRL+C. User can interrupt FPGA configuration by pressing CTRL+C.
config SYS_FPGA_PROG_FEEDBACK
bool "Progress output during FPGA configuration"
depends on FPGA
default y if FPGA_VIRTEX2
help
Enable printing of hash marks during FPGA configuration.
endmenu endmenu

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@ -15,7 +15,6 @@
#endif #endif
#undef CONFIG_SYS_FPGA_CHECK_BUSY #undef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
/* Note: The assumption is that we cannot possibly run fast enough to /* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz). * overrun the device (the Slave Parallel mode can free run at 50MHz).

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@ -41,10 +41,6 @@
#define CONFIG_FPGA_DELAY() #define CONFIG_FPGA_DELAY()
#endif #endif
#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#endif
/* /*
* Check for errors during configuration by default * Check for errors during configuration by default
*/ */

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@ -131,7 +131,6 @@
* it needs non-blocking CFI routines. * it needs non-blocking CFI routines.
*/ */
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000 #define CONFIG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */ /* End of user parameters to be customized */

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@ -743,7 +743,6 @@ CONFIG_SYS_FPGA_FTIM0
CONFIG_SYS_FPGA_FTIM1 CONFIG_SYS_FPGA_FTIM1
CONFIG_SYS_FPGA_FTIM2 CONFIG_SYS_FPGA_FTIM2
CONFIG_SYS_FPGA_FTIM3 CONFIG_SYS_FPGA_FTIM3
CONFIG_SYS_FPGA_PROG_FEEDBACK
CONFIG_SYS_FPGA_SIZE CONFIG_SYS_FPGA_SIZE
CONFIG_SYS_FPGA_WAIT CONFIG_SYS_FPGA_WAIT
CONFIG_SYS_FSL_BMAN_ADDR CONFIG_SYS_FSL_BMAN_ADDR