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imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint

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The new stable configuration is missing the 100mt setpoint, remove
it before updating the config to make sure the changes are separated
cleanly.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Frieder Schrempf 2022-08-24 15:59:12 +02:00 committed by Stefano Babic
parent 890022f0cf
commit 8dd0924ea0
3 changed files with 1 additions and 54 deletions
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4
arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
View File

@ -46,10 +46,6 @@
ddrc_opp_table: opp-table { ddrc_opp_table: opp-table {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M { opp-100M {
opp-hz = /bits/ 64 <100000000>; opp-hz = /bits/ 64 <100000000>;
}; };

49
board/kontron/sl-mx8mm/lpddr4_timing.c
View File

@ -1121,46 +1121,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
/* P2 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
{ 0x5400d, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x4d },
{ 0x54036, 0x4d },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3100 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */ /* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = { struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 }, { 0xd0000, 0x0 },
@ -1812,13 +1772,6 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg = ddr_fsp1_cfg, .fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
}, },
{
/* P2 100mts 1D */
.drate = 100,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp2_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{ {
/* P0 3000mts 2D */ /* P0 3000mts 2D */
.drate = 3000, .drate = 3000,
@ -1840,5 +1793,5 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie, .ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, }, .fsp_table = { 3000, 400, },
}; };

2
board/kontron/sl-mx8mm/spl.c
View File

@ -95,8 +95,6 @@ static void spl_dram_init(void)
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1; dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110; dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1; dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
if (!ddr_init(&dram_timing)) { if (!ddr_init(&dram_timing)) {
if (check_ram_available(SZ_2G)) if (check_ram_available(SZ_2G))