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Merge branch '2022-04-08-Kconfig-updates-and-dead-code-removal'

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- Migration of more symbols from board config.h files to defconfig
- Remove unused network drivers
This commit is contained in:
Tom Rini 2022-04-08 13:33:14 -04:00
commit 909d2120e2
292 changed files with 424 additions and 11098 deletions
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17
Kconfig
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@ -395,6 +395,23 @@ config BUILD_TARGET
special image will be automatically built upon calling
make / buildman.
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
default y if RCAR_GEN3
help
In some cases, we need to enforce a hard limit on how big the U-Boot
image itself can be.
config BOARD_SIZE_LIMIT
int "Maximum size of the U-Boot image in bytes"
default 1048576 if RCAR_GEN3
depends on HAS_BOARD_SIZE_LIMIT
help
Maximum size of the U-Boot image. When defined, the build system
checks that the actual size does not exceed it. This does not
include SPL nor TPL, on platforms that use that functionality, they
have a separate option to restict size.
config SYS_CUSTOM_LDSCRIPT
bool "Use a custom location for the U-Boot linker script"
help

16
README
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@ -487,9 +487,6 @@ The following options need to be configured:
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
CONFIG_SYS_FSL_HAS_DP_DDR
Defines the SoC has DP-DDR used for DPAA.
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
@ -1532,14 +1529,6 @@ The following options need to be configured:
of the backslashes before semicolons and special
symbols.
- Command Line Editing and History:
CONFIG_CMDLINE_PS_SUPPORT
Enable support for changing the command prompt string
at run-time. Only static string is supported so far.
The string is obtained from environment variables PS1
and PS2.
- Default Environment:
CONFIG_EXTRA_ENV_SETTINGS
@ -2183,11 +2172,6 @@ use the "saveenv" command to store a valid environment.
later, once stdio is running and output goes to the LCD, if
present.
- CONFIG_BOARD_SIZE_LIMIT:
Maximum size of the U-Boot image. When defined, the
build system checks that the actual size does not
exceed it.
Low Level (hardware related) configuration options:
---------------------------------------------------

1
arch/arm/cpu/arm920t/Makefile
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@ -7,7 +7,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
# some files can only build in ARM mode

19
arch/arm/cpu/arm920t/ep93xx/Makefile
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@ -1,19 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Cirrus Logic EP93xx CPU-specific Makefile
#
# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
#
# Copyright (C) 2004, 2005
# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
#
# Copyright (C) 2006
# Dominic Rath <Dominic.Rath@gmx.de>
#
# Based on an original Makefile, which is
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = cpu.o led.o speed.o timer.o
obj-y += lowlevel_init.o

37
arch/arm/cpu/arm920t/ep93xx/cpu.c
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@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx CPU-specific support.
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
extern void reset_cpu(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
uint32_t value;
/* Unlock DeviceCfg and set SWRST */
writel(0xAA, &syscon->sysswlock);
value = readl(&syscon->devicecfg);
value |= SYSCON_DEVICECFG_SWRST;
writel(value, &syscon->devicecfg);
/* Unlock DeviceCfg and clear SWRST */
writel(0xAA, &syscon->sysswlock);
value = readl(&syscon->devicecfg);
value &= ~SYSCON_DEVICECFG_SWRST;
writel(value, &syscon->devicecfg);
/* Dying... */
while (1)
; /* noop */
}

85
arch/arm/cpu/arm920t/ep93xx/led.c
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@ -1,85 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*/
#include <asm/io.h>
#include <asm/arch/ep93xx.h>
#include <config.h>
#include <status_led.h>
static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
1 << CONFIG_LED_STATUS_RED};
static inline void switch_LED_on(uint8_t led)
{
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
saved_state[led] = CONFIG_LED_STATUS_ON;
}
static inline void switch_LED_off(uint8_t led)
{
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
saved_state[led] = CONFIG_LED_STATUS_OFF;
}
void red_led_on(void)
{
switch_LED_on(CONFIG_LED_STATUS_RED);
}
void red_led_off(void)
{
switch_LED_off(CONFIG_LED_STATUS_RED);
}
void green_led_on(void)
{
switch_LED_on(CONFIG_LED_STATUS_GREEN);
}
void green_led_off(void)
{
switch_LED_off(CONFIG_LED_STATUS_GREEN);
}
void __led_init(led_id_t mask, int state)
{
__led_set(mask, state);
}
void __led_toggle(led_id_t mask)
{
if (CONFIG_LED_STATUS_RED == mask) {
if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
red_led_off();
else
red_led_on();
} else if (CONFIG_LED_STATUS_GREEN == mask) {
if (CONFIG_LED_STATUS_ON ==
saved_state[CONFIG_LED_STATUS_GREEN])
green_led_off();
else
green_led_on();
}
}
void __led_set(led_id_t mask, int state)
{
if (CONFIG_LED_STATUS_RED == mask) {
if (CONFIG_LED_STATUS_ON == state)
red_led_on();
else
red_led_off();
} else if (CONFIG_LED_STATUS_GREEN == mask) {
if (CONFIG_LED_STATUS_ON == state)
green_led_on();
else
green_led_off();
}
}

457
arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
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@ -1,457 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Low-level initialization for EP93xx
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2013
* Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
* Copyright (C) 2006 Cirrus Logic Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <config.h>
#include <asm/arch-ep93xx/ep93xx.h>
/*
/* Configure the SDRAM based on the supplied settings.
*
* Input: r0 - SDRAM DEVCFG register
* r2 - configuration for SDRAM chips
* Output: none
* Modifies: r3, r4
*/
ep93xx_sdram_config:
/* Program the SDRAM device configuration register. */
ldr r3, =SDRAM_BASE
#ifdef CONFIG_EDB93XX_SDCS0
str r0, [r3, #SDRAM_OFF_DEVCFG0]
#endif
#ifdef CONFIG_EDB93XX_SDCS1
str r0, [r3, #SDRAM_OFF_DEVCFG1]
#endif
#ifdef CONFIG_EDB93XX_SDCS2
str r0, [r3, #SDRAM_OFF_DEVCFG2]
#endif
#ifdef CONFIG_EDB93XX_SDCS3
str r0, [r3, #SDRAM_OFF_DEVCFG3]
#endif
/* Set the Initialize and MRS bits (issue continuous NOP commands
* (INIT & MRS set))
*/
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Delay for 200us. */
mov r4, #0x3000
delay1:
subs r4, r4, #1
bne delay1
/* Clear the MRS bit to issue a precharge all. */
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Temporarily set the refresh timer to 0x10. Make it really low so
* that refresh cycles are generated.
*/
ldr r4, =0x10
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
/* Delay for at least 80 SDRAM clock cycles. */
mov r4, #80
delay2:
subs r4, r4, #1
bne delay2
/* Set the refresh timer to the fastest required for any device
* that might be used. Set 9.6 ms refresh time.
*/
ldr r4, =0x01e0
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
/* Select mode register update mode. */
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Program the mode register on the SDRAM by performing fake read */
ldr r4, [r2]
/* Select normal operating mode. */
ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Return to the caller. */
mov pc, lr
/*
* Test to see if the SDRAM has been configured in a usable mode.
*
* Input: r0 - Test address of SDRAM
* Output: r0 - 0 -- Test OK, -1 -- Failed
* Modifies: r0-r5
*/
ep93xx_sdram_test:
/* Load the test patterns to be written to SDRAM. */
ldr r1, =0xf00dface
ldr r2, =0xdeadbeef
ldr r3, =0x08675309
ldr r4, =0xdeafc0ed
/* Store the test patterns to SDRAM. */
stmia r0, {r1-r4}
/* Load the test patterns from SDRAM one at a time and compare them
* to the actual pattern.
*/
ldr r5, [r0]
cmp r5, r1
ldreq r5, [r0, #0x0004]
cmpeq r5, r2
ldreq r5, [r0, #0x0008]
cmpeq r5, r3
ldreq r5, [r0, #0x000c]
cmpeq r5, r4
/* Return -1 if a mismatch was encountered, 0 otherwise. */
mvnne r0, #0xffffffff
moveq r0, #0x00000000
/* Return to the caller. */
mov pc, lr
/*
* Determine the size of the SDRAM. Use data=address for the scan.
*
* Input: r0 - Start SDRAM address
* Return: r0 - Single block size
* r1 - Valid block mask
* r2 - Total block count
* Modifies: r0-r5
*/
ep93xx_sdram_size:
/* Store zero at offset zero. */
str r0, [r0]
/* Start checking for an alias at 1MB into SDRAM. */
ldr r1, =0x00100000
/* Store the offset at the current offset. */
check_block_size:
str r1, [r0, r1]
/* Read back from zero. */
ldr r2, [r0]
/* Stop searching of an alias was found. */
cmp r1, r2
beq found_block_size
/* Advance to the next power of two boundary. */
mov r1, r1, lsl #1
/* Loop back if the size has not reached 256MB. */
cmp r1, #0x10000000
bne check_block_size
/* A full 256MB of memory was found, so return it now. */
ldr r0, =0x10000000
ldr r1, =0x00000000
ldr r2, =0x00000001
mov pc, lr
/* An alias was found. See if the first block is 128MB in size. */
found_block_size:
cmp r1, #0x08000000
/* The first block is 128MB, so there is no further memory. Return it
* now.
*/
ldreq r0, =0x08000000
ldreq r1, =0x00000000
ldreq r2, =0x00000001
moveq pc, lr
/* Save the block size, set the block address bits to zero, and
* initialize the block count to one.
*/
mov r3, r1
ldr r4, =0x00000000
ldr r5, =0x00000001
/* Look for additional blocks of memory by searching for non-aliases. */
find_blocks:
/* Store zero back to address zero. It may be overwritten. */
str r0, [r0]
/* Advance to the next power of two boundary. */
mov r1, r1, lsl #1
/* Store the offset at the current offset. */
str r1, [r0, r1]
/* Read back from zero. */
ldr r2, [r0]
/* See if a non-alias was found. */
cmp r1, r2
/* If a non-alias was found, then or in the block address bit and
* multiply the block count by two (since there are two unique
* blocks, one with this bit zero and one with it one).
*/
orrne r4, r4, r1
movne r5, r5, lsl #1
/* Continue searching if there are more address bits to check. */
cmp r1, #0x08000000
bne find_blocks
/* Return the block size, address mask, and count. */
mov r0, r3
mov r1, r4
mov r2, r5
/* Return to the caller. */
mov pc, lr
.globl lowlevel_init
lowlevel_init:
mov r6, lr
/* Make sure caches are off and invalidated. */
ldr r0, =0x00000000
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
nop
nop
/* Turn off the green LED and turn on the red LED. If the red LED
* is left on for too long, the external reset circuit described
* by application note AN258 will cause the system to reset.
*/
ldr r1, =EP93XX_LED_DATA
ldr r0, [r1]
bic r0, r0, #EP93XX_LED_GREEN_ON
orr r0, r0, #EP93XX_LED_RED_ON
str r0, [r1]
/* Undo the silly static memory controller programming performed
* by the boot rom.
*/
ldr r0, =SMC_BASE
/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
ldr r1, =0x0000fbe0
/* Reset EP93XX_OFF_SMCBCR0 */
ldr r2, [r0]
orr r2, r2, r1
str r2, [r0]
ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR1]
ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR2]
ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR3]
ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR6]
ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR7]
/* Set the PLL1 and processor clock. */
ldr r0, =SYSCON_BASE
#ifdef CONFIG_EDB9301
/* 332MHz, giving a 166MHz processor clock. */
ldr r1, = 0x02b49907
#else
#ifdef CONFIG_EDB93XX_INDUSTRIAL
/* 384MHz, giving a 196MHz processor clock. */
ldr r1, =0x02a4bb38
#else
/* 400MHz, giving a 200MHz processor clock. */
ldr r1, =0x02a4e39e
#endif
#endif
str r1, [r0, #SYSCON_OFF_CLKSET1]
nop
nop
nop
nop
nop
/* Need to make sure that SDRAM is configured correctly before
* coping the code into it.
*/
#ifdef CONFIG_EDB93XX_SDCS0
mov r11, #SDRAM_DEVCFG0_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS1
mov r11, #SDRAM_DEVCFG1_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS2
mov r11, #SDRAM_DEVCFG2_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS3
ldr r0, =SYSCON_BASE
ldr r0, [r0, #SYSCON_OFF_SYSCFG]
ands r0, r0, #SYSCON_SYSCFG_LASDO
moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
movne r11, #SDRAM_DEVCFG3_ASD1_BASE
#endif
/* See Table 13-5 in EP93xx datasheet for more info about DRAM
* register mapping */
/* Try a 32-bit wide configuration of SDRAM. */
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
/* Set burst count: 4 and CAS: 2
* Burst mode [A11:A10]; CAS [A16:A14]
*/
orr r2, r11, #0x00008800
bl ep93xx_sdram_config
/* Test the SDRAM. */
mov r0, r11
bl ep93xx_sdram_test
cmp r0, #0x00000000
beq ep93xx_sdram_done
/* Try a 16-bit wide configuration of SDRAM. */
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
/* Set burst count: 8, CAS: 2, sequential burst
* Accoring to Table 13-3 for 16bit operations mapping must be shifted.
* Burst mode [A10:A9]; CAS [A15:A13]
*/
orr r2, r11, #0x00004600
bl ep93xx_sdram_config
/* Test the SDRAM. */
mov r0, r11
bl ep93xx_sdram_test
cmp r0, #0x00000000
beq ep93xx_sdram_done
/* Turn off the red LED. */
ldr r0, =EP93XX_LED_DATA
ldr r1, [r0]
bic r1, r1, #EP93XX_LED_RED_ON
str r1, [r0]
/* There is no SDRAM so flash the green LED. */
flash_green:
orr r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_1:
subs r2, r2, #1
bne flash_green_delay_1
bic r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_2:
subs r2, r2, #1
bne flash_green_delay_2
orr r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_3:
subs r2, r2, #1
bne flash_green_delay_3
bic r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00050000
flash_green_delay_4:
subs r2, r2, #1
bne flash_green_delay_4
b flash_green
ep93xx_sdram_done:
ldr r1, =EP93XX_LED_DATA
ldr r0, [r1]
bic r0, r0, #EP93XX_LED_RED_ON
str r0, [r1]
/* Determine the size of the SDRAM. */
mov r0, r11
bl ep93xx_sdram_size
/* Save the SDRAM characteristics. */
mov r8, r0
mov r9, r1
mov r10, r2
/* Compute total memory size into r1 */
mul r1, r8, r10
#ifdef CONFIG_EDB93XX_SDCS0
ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
#endif
#ifdef CONFIG_EDB93XX_SDCS1
ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
#endif
#ifdef CONFIG_EDB93XX_SDCS2
ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
#endif
#ifdef CONFIG_EDB93XX_SDCS3
ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
#endif
/* Consider small DRAM size as:
* < 32Mb for 32bit bus
* < 64Mb for 16bit bus
*/
tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
moveq r1, r1, lsr #1
cmp r1, #0x02000000
#if defined(CONFIG_EDB9301)
/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
movlt r1, #0x03f0
movge r1, #0x01e0
#else
/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
movlt r1, #0x0600
movge r1, #0x2f0
#endif
str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
/* Save the memory configuration information. */
orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
stmia r0, {r8-r11}
mov lr, r6
mov pc, lr

96
arch/arm/cpu/arm920t/ep93xx/speed.c
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@ -1,96 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx PLL support.
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
/*
* get_board_sys_clk() should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/*
* return the PLL output frequency
*
* PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
* / (X2IPD + 1) / 2^PS
*/
static ulong get_PLLCLK(uint32_t *pllreg)
{
uint8_t i;
const uint32_t clkset = readl(pllreg);
uint64_t rate = get_board_sys_clk();
rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
rate >>= 1;
return (ulong)rate;
}
/* return FCLK frequency */
ulong get_FCLK(void)
{
const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
const uint32_t clkset1 = readl(&syscon->clkset1);
const uint8_t fclk_div =
fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
return fclk_rate;
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
const uint32_t clkset1 = readl(&syscon->clkset1);
const uint8_t hclk_div =
hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
return hclk_rate;
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
const uint32_t clkset1 = readl(&syscon->clkset1);
const uint8_t pclk_div =
pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
const ulong pclk_rate = get_HCLK() / pclk_div;
return pclk_rate;
}
/* return UCLK frequency */
ulong get_UCLK(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
ulong uclk_rate;
const uint32_t value = readl(&syscon->pwrcnt);
if (value & SYSCON_PWRCNT_UART_BAUD)
uclk_rate = get_board_sys_clk();
else
uclk_rate = get_board_sys_clk() / 2;
return uclk_rate;
}

117
arch/arm/cpu/arm920t/ep93xx/timer.c
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@ -1,117 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx timer support.
*
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*
* Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
* author unknown.
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
#define TIMER_CLKSEL (1 << 3)
#define TIMER_ENABLE (1 << 7)
#define TIMER_FREQ 508469 /* ticks / second */
#define TIMER_MAX_VAL 0xFFFFFFFF
static struct ep93xx_timer
{
unsigned long long ticks;
unsigned long last_read;
} timer;
static inline unsigned long long usecs_to_ticks(unsigned long usecs)
{
unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
do_div(ticks, 1000 * 1000);
return ticks;
}
static inline void read_timer(void)
{
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
if (now >= timer.last_read)
timer.ticks += now - timer.last_read;
else
/* an overflow occurred */
timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
timer.last_read = now;
}
/*
* Get the number of ticks (in CONFIG_SYS_HZ resolution)
*/
unsigned long long get_ticks(void)
{
unsigned long long sys_ticks;
read_timer();
sys_ticks = timer.ticks * CONFIG_SYS_HZ;
do_div(sys_ticks, TIMER_FREQ);
return sys_ticks;
}
unsigned long get_timer(unsigned long base)
{
return get_ticks() - base;
}
void __udelay(unsigned long usec)
{
unsigned long long target;
read_timer();
target = timer.ticks + usecs_to_ticks(usec);
while (timer.ticks < target)
read_timer();
}
int timer_init(void)
{
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
/* use timer 3 with 508KHz and free running, not enabled now */
writel(TIMER_CLKSEL, &timer_regs->timer3.control);
/* set initial timer value */
writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
/* Enable the timer */
writel(TIMER_ENABLE | TIMER_CLKSEL,
&timer_regs->timer3.control);
/* Reset the timer */
read_timer();
timer.ticks = 0;
return 0;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
unsigned long get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

25
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -502,6 +502,31 @@ config SYS_FSL_HAS_CCN508
config SYS_FSL_HAS_DP_DDR
bool
help
Defines the SoC has DP-DDR used for DPAA.
config DP_DDR_CTRL
int
depends on SYS_FSL_HAS_DP_DDR
default 2 if ARCH_LS2080A
config DP_DDR_NUM_CTRLS
int
depends on SYS_FSL_HAS_DP_DDR
default 1 if ARCH_LS2080A
config SYS_DP_DDR_BASE
hex
depends on SYS_FSL_HAS_DP_DDR
default 0x6000000000 if ARCH_LS2080A
config SYS_DP_DDR_BASE_PHY
int
depends on SYS_FSL_HAS_DP_DDR
default 0 if ARCH_LS2080A
help
DDR controller uses this value as the base address for binding.
It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
config SYS_FSL_SRDS_1
bool

666
arch/arm/include/asm/arch-ep93xx/ep93xx.h
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@ -1,666 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Cirrus Logic EP93xx register definitions.
*
* Copyright (C) 2013
* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
*
* Copyright (C) 2009
* Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2006
* Dominic Rath <Dominic.Rath@gmx.de>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*
* Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
*
* Copyright (C) 2004 Ray Lehtiniemi
* Copyright (C) 2003 Cirrus Logic, Inc
* Copyright (C) 1999 ARM Limited.
*/
#define EP93XX_AHB_BASE 0x80000000
#define EP93XX_APB_BASE 0x80800000
/*
* 0x80000000 - 0x8000FFFF: DMA
*/
#define DMA_OFFSET 0x000000
#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
#ifndef __ASSEMBLY__
struct dma_channel {
uint32_t control;
uint32_t interrupt;
uint32_t ppalloc;
uint32_t status;
uint32_t reserved0;
uint32_t remain;
uint32_t reserved1[2];
uint32_t maxcnt0;
uint32_t base0;
uint32_t current0;
uint32_t reserved2;
uint32_t maxcnt1;
uint32_t base1;
uint32_t current1;
uint32_t reserved3;
};
struct dma_regs {
struct dma_channel m2p_channel_0;
struct dma_channel m2p_channel_1;
struct dma_channel m2p_channel_2;
struct dma_channel m2p_channel_3;
struct dma_channel m2m_channel_0;
struct dma_channel m2m_channel_1;
struct dma_channel reserved0[2];
struct dma_channel m2p_channel_5;
struct dma_channel m2p_channel_4;
struct dma_channel m2p_channel_7;
struct dma_channel m2p_channel_6;
struct dma_channel m2p_channel_9;
struct dma_channel m2p_channel_8;
uint32_t channel_arbitration;
uint32_t reserved[15];
uint32_t global_interrupt;
};
#endif
/*
* 0x80010000 - 0x8001FFFF: Ethernet MAC
*/
#define MAC_OFFSET 0x010000
#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
#ifndef __ASSEMBLY__
struct mac_queue {
uint32_t badd;
union { /* deal with half-word aligned registers */
uint32_t blen;
union {
uint16_t filler;
uint16_t curlen;
};
};
uint32_t curadd;
};
struct mac_regs {
uint32_t rxctl;
uint32_t txctl;
uint32_t testctl;
uint32_t reserved0;
uint32_t miicmd;
uint32_t miidata;
uint32_t miists;
uint32_t reserved1;
uint32_t selfctl;
uint32_t inten;
uint32_t intstsp;
uint32_t intstsc;
uint32_t reserved2[2];
uint32_t diagad;
uint32_t diagdata;
uint32_t gt;
uint32_t fct;
uint32_t fcf;
uint32_t afp;
union {
struct {
uint32_t indad;
uint32_t indad_upper;
};
uint32_t hashtbl;
};
uint32_t reserved3[2];
uint32_t giintsts;
uint32_t giintmsk;
uint32_t giintrosts;
uint32_t giintfrc;
uint32_t txcollcnt;
uint32_t rxmissnct;
uint32_t rxruntcnt;
uint32_t reserved4;
uint32_t bmctl;
uint32_t bmsts;
uint32_t rxbca;
uint32_t reserved5;
struct mac_queue rxdq;
uint32_t rxdqenq;
struct mac_queue rxstsq;
uint32_t rxstsqenq;
struct mac_queue txdq;
uint32_t txdqenq;
struct mac_queue txstsq;
uint32_t reserved6;
uint32_t rxbufthrshld;
uint32_t txbufthrshld;
uint32_t rxststhrshld;
uint32_t txststhrshld;
uint32_t rxdthrshld;
uint32_t txdthrshld;
uint32_t maxfrmlen;
uint32_t maxhdrlen;
};
#endif
#define SELFCTL_RWP (1 << 7)
#define SELFCTL_GPO0 (1 << 5)
#define SELFCTL_PUWE (1 << 4)
#define SELFCTL_PDWE (1 << 3)
#define SELFCTL_MIIL (1 << 2)
#define SELFCTL_RESET (1 << 0)
#define INTSTS_RWI (1 << 30)
#define INTSTS_RXMI (1 << 29)
#define INTSTS_RXBI (1 << 28)
#define INTSTS_RXSQI (1 << 27)
#define INTSTS_TXLEI (1 << 26)
#define INTSTS_ECIE (1 << 25)
#define INTSTS_TXUHI (1 << 24)
#define INTSTS_MOI (1 << 18)
#define INTSTS_TXCOI (1 << 17)
#define INTSTS_RXROI (1 << 16)
#define INTSTS_MIII (1 << 12)
#define INTSTS_PHYI (1 << 11)
#define INTSTS_TI (1 << 10)
#define INTSTS_AHBE (1 << 8)
#define INTSTS_OTHER (1 << 4)
#define INTSTS_TXSQ (1 << 3)
#define INTSTS_RXSQ (1 << 2)
#define BMCTL_MT (1 << 13)
#define BMCTL_TT (1 << 12)
#define BMCTL_UNH (1 << 11)
#define BMCTL_TXCHR (1 << 10)
#define BMCTL_TXDIS (1 << 9)
#define BMCTL_TXEN (1 << 8)
#define BMCTL_EH2 (1 << 6)
#define BMCTL_EH1 (1 << 5)
#define BMCTL_EEOB (1 << 4)
#define BMCTL_RXCHR (1 << 2)
#define BMCTL_RXDIS (1 << 1)
#define BMCTL_RXEN (1 << 0)
#define BMSTS_TXACT (1 << 7)
#define BMSTS_TP (1 << 4)
#define BMSTS_RXACT (1 << 3)
#define BMSTS_QID_MASK 0x07
#define BMSTS_QID_RXDATA 0x00
#define BMSTS_QID_TXDATA 0x01
#define BMSTS_QID_RXSTS 0x02
#define BMSTS_QID_TXSTS 0x03
#define BMSTS_QID_RXDESC 0x04
#define BMSTS_QID_TXDESC 0x05
#define AFP_MASK 0x07
#define AFP_IAPRIMARY 0x00
#define AFP_IASECONDARY1 0x01
#define AFP_IASECONDARY2 0x02
#define AFP_IASECONDARY3 0x03
#define AFP_TX 0x06
#define AFP_HASH 0x07
#define RXCTL_PAUSEA (1 << 20)
#define RXCTL_RXFCE1 (1 << 19)
#define RXCTL_RXFCE0 (1 << 18)
#define RXCTL_BCRC (1 << 17)
#define RXCTL_SRXON (1 << 16)
#define RXCTL_RCRCA (1 << 13)
#define RXCTL_RA (1 << 12)
#define RXCTL_PA (1 << 11)
#define RXCTL_BA (1 << 10)
#define RXCTL_MA (1 << 9)
#define RXCTL_IAHA (1 << 8)
#define RXCTL_IA3 (1 << 3)
#define RXCTL_IA2 (1 << 2)
#define RXCTL_IA1 (1 << 1)
#define RXCTL_IA0 (1 << 0)
#define TXCTL_DEFDIS (1 << 7)
#define TXCTL_MBE (1 << 6)
#define TXCTL_ICRC (1 << 5)
#define TXCTL_TPD (1 << 4)
#define TXCTL_OCOLL (1 << 3)
#define TXCTL_SP (1 << 2)
#define TXCTL_PB (1 << 1)
#define TXCTL_STXON (1 << 0)
#define MIICMD_REGAD_MASK (0x001F)
#define MIICMD_PHYAD_MASK (0x03E0)
#define MIICMD_OPCODE_MASK (0xC000)
#define MIICMD_PHYAD_8950 (0x0000)
#define MIICMD_OPCODE_READ (0x8000)
#define MIICMD_OPCODE_WRITE (0x4000)
#define MIISTS_BUSY (1 << 0)
/*
* 0x80020000 - 0x8002FFFF: USB OHCI
*/
#define USB_OFFSET 0x020000
#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
/*
* 0x80030000 - 0x8003FFFF: Raster engine
*/
#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
#define RASTER_OFFSET 0x030000
#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
#endif
/*
* 0x80040000 - 0x8004FFFF: Graphics accelerator
*/
#if defined(CONFIG_EP9315)
#define GFX_OFFSET 0x040000
#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
#endif
/*
* 0x80050000 - 0x8005FFFF: Reserved
*/
/*
* 0x80060000 - 0x8006FFFF: SDRAM controller
*/
#define SDRAM_OFFSET 0x060000
#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
#ifndef __ASSEMBLY__
struct sdram_regs {
uint32_t reserved;
uint32_t glconfig;
uint32_t refrshtimr;
uint32_t bootsts;
uint32_t devcfg0;
uint32_t devcfg1;
uint32_t devcfg2;
uint32_t devcfg3;
};
#endif
#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
#define SDRAM_DEVCFG_SROMLL (1 << 5)
#define SDRAM_DEVCFG_CASLAT_2 0x00010000
#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
#define SDRAM_OFF_GLCONFIG 0x0004
#define SDRAM_OFF_REFRSHTIMR 0x0008
#define SDRAM_OFF_DEVCFG0 0x0010
#define SDRAM_OFF_DEVCFG1 0x0014
#define SDRAM_OFF_DEVCFG2 0x0018
#define SDRAM_OFF_DEVCFG3 0x001C
#define SDRAM_DEVCFG0_BASE 0xC0000000
#define SDRAM_DEVCFG1_BASE 0xD0000000
#define SDRAM_DEVCFG2_BASE 0xE0000000
#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
#define GLCONFIG_INIT (1 << 0)
#define GLCONFIG_MRS (1 << 1)
#define GLCONFIG_SMEMBUSY (1 << 5)
#define GLCONFIG_LCR (1 << 6)
#define GLCONFIG_REARBEN (1 << 7)
#define GLCONFIG_CLKSHUTDOWN (1 << 30)
#define GLCONFIG_CKE (1 << 31)
#define EP93XX_SDRAMCTRL 0x80060000
#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
/*
* 0x80070000 - 0x8007FFFF: Reserved
*/
/*
* 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
*/
#define SMC_OFFSET 0x080000
#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
#ifndef __ASSEMBLY__
struct smc_regs {
uint32_t bcr0;
uint32_t bcr1;
uint32_t bcr2;
uint32_t bcr3;
uint32_t reserved0[2];
uint32_t bcr6;
uint32_t bcr7;
#if defined(CONFIG_EP9315)
uint32_t pcattribute;
uint32_t pccommon;
uint32_t pcio;
uint32_t reserved1[5];
uint32_t pcmciactrl;
#endif
};
#endif
#define EP93XX_OFF_SMCBCR0 0x00
#define EP93XX_OFF_SMCBCR1 0x04
#define EP93XX_OFF_SMCBCR2 0x08
#define EP93XX_OFF_SMCBCR3 0x0C
#define EP93XX_OFF_SMCBCR6 0x18
#define EP93XX_OFF_SMCBCR7 0x1C
#define SMC_BCR_IDCY_SHIFT 0
#define SMC_BCR_WST1_SHIFT 5
#define SMC_BCR_BLE (1 << 10)
#define SMC_BCR_WST2_SHIFT 11
#define SMC_BCR_MW_SHIFT 28
/*
* 0x80090000 - 0x8009FFFF: Boot ROM
*/
/*
* 0x800A0000 - 0x800AFFFF: IDE interface
*/
/*
* 0x800B0000 - 0x800BFFFF: VIC1
*/
/*
* 0x800C0000 - 0x800CFFFF: VIC2
*/
/*
* 0x800D0000 - 0x800FFFFF: Reserved
*/
/*
* 0x80800000 - 0x8080FFFF: Reserved
*/
/*
* 0x80810000 - 0x8081FFFF: Timers
*/
#define TIMER_OFFSET 0x010000
#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
#ifndef __ASSEMBLY__
struct timer {
uint32_t load;
uint32_t value;
uint32_t control;
uint32_t clear;
};
struct timer4 {
uint32_t value_low;
uint32_t value_high;
};
struct timer_regs {
struct timer timer1;
uint32_t reserved0[4];
struct timer timer2;
uint32_t reserved1[12];
struct timer4 timer4;
uint32_t reserved2[6];
struct timer timer3;
};
#endif
/*
* 0x80820000 - 0x8082FFFF: I2S
*/
#define I2S_OFFSET 0x020000
#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
/*
* 0x80830000 - 0x8083FFFF: Security
*/
#define SECURITY_OFFSET 0x030000
#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
#define EXTENSIONID (SECURITY_BASE + 0x2714)
/*
* 0x80840000 - 0x8084FFFF: GPIO
*/
#define GPIO_OFFSET 0x040000
#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
#ifndef __ASSEMBLY__
struct gpio_int {
uint32_t inttype1;
uint32_t inttype2;
uint32_t eoi;
uint32_t inten;
uint32_t intsts;
uint32_t rawintsts;
uint32_t db;
};
struct gpio_regs {
uint32_t padr;
uint32_t pbdr;
uint32_t pcdr;
uint32_t pddr;
uint32_t paddr;
uint32_t pbddr;
uint32_t pcddr;
uint32_t pdddr;
uint32_t pedr;
uint32_t peddr;
uint32_t reserved0[2];
uint32_t pfdr;
uint32_t pfddr;
uint32_t pgdr;
uint32_t pgddr;
uint32_t phdr;
uint32_t phddr;
uint32_t reserved1;
uint32_t finttype1;
uint32_t finttype2;
uint32_t reserved2;
struct gpio_int pfint;
uint32_t reserved3[10];
struct gpio_int paint;
struct gpio_int pbint;
uint32_t eedrive;
};
#endif
#define EP93XX_LED_DATA 0x80840020
#define EP93XX_LED_GREEN_ON 0x0001
#define EP93XX_LED_RED_ON 0x0002
#define EP93XX_LED_DDR 0x80840024
#define EP93XX_LED_GREEN_ENABLE 0x0001
#define EP93XX_LED_RED_ENABLE 0x00020000
/*
* 0x80850000 - 0x8087FFFF: Reserved
*/
/*
* 0x80880000 - 0x8088FFFF: AAC
*/
#define AAC_OFFSET 0x080000
#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
/*
* 0x80890000 - 0x8089FFFF: Reserved
*/
/*
* 0x808A0000 - 0x808AFFFF: SPI
*/
#define SPI_OFFSET 0x0A0000
#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
/*
* 0x808B0000 - 0x808BFFFF: IrDA
*/
#define IRDA_OFFSET 0x0B0000
#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
/*
* 0x808C0000 - 0x808CFFFF: UART1
*/
#define UART1_OFFSET 0x0C0000
#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
/*
* 0x808D0000 - 0x808DFFFF: UART2
*/
#define UART2_OFFSET 0x0D0000
#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
/*
* 0x808E0000 - 0x808EFFFF: UART3
*/
#define UART3_OFFSET 0x0E0000
#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
/*
* 0x808F0000 - 0x808FFFFF: Key Matrix
*/
#define KEY_OFFSET 0x0F0000
#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
/*
* 0x80900000 - 0x8090FFFF: Touchscreen
*/
#define TOUCH_OFFSET 0x900000
#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
/*
* 0x80910000 - 0x8091FFFF: Pulse Width Modulation
*/
#define PWM_OFFSET 0x910000
#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
/*
* 0x80920000 - 0x8092FFFF: Real time clock
*/
#define RTC_OFFSET 0x920000
#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
/*
* 0x80930000 - 0x8093FFFF: Syscon
*/
#define SYSCON_OFFSET 0x930000
#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
/* Security */
#define SECURITY_EXTENSIONID 0x80832714
#ifndef __ASSEMBLY__
struct syscon_regs {
uint32_t pwrsts;
uint32_t pwrcnt;
uint32_t halt;
uint32_t stby;
uint32_t reserved0[2];
uint32_t teoi;
uint32_t stfclr;
uint32_t clkset1;
uint32_t clkset2;
uint32_t reserved1[6];
uint32_t scratch0;
uint32_t scratch1;
uint32_t reserved2[2];
uint32_t apbwait;
uint32_t bustmstrarb;
uint32_t bootmodeclr;
uint32_t reserved3[9];
uint32_t devicecfg;
uint32_t vidclkdiv;
uint32_t mirclkdiv;
uint32_t i2sclkdiv;
uint32_t keytchclkdiv;
uint32_t chipid;
uint32_t reserved4;
uint32_t syscfg;
uint32_t reserved5[8];
uint32_t sysswlock;
};
#else
#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
#endif
#define SYSCON_OFF_CLKSET1 0x0020
#define SYSCON_OFF_SYSCFG 0x009c
#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
#define SYSCON_PWRCNT_USH_EN (1 << 28)
#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
#define SYSCON_CLKSET_PLL_PS_SHIFT 16
#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
#define SYSCON_CLKSET1_NBYP1 (1 << 23)
#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
#define SYSCON_CLKSET2_NBYP2 (1 << 19)
#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
#define SYSCON_CHIPID_REV_MASK 0xF0000000
#define SYSCON_DEVICECFG_SWRST (1 << 31)
#define SYSCON_SYSCFG_LASDO 0x00000020
/*
* 0x80930000 - 0x8093FFFF: Watchdog Timer
*/
#define WATCHDOG_OFFSET 0x940000
#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
/*
* 0x80950000 - 0x9000FFFF: Reserved
*/
/*
* During low_level init we store memory layout in memory at specific location
*/
#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008

1
arch/arm/mach-at91/arm926ejs/Makefile
View File

@ -16,7 +16,6 @@ obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o

47
arch/arm/mach-at91/arm926ejs/led.c
View File

@ -1,47 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <status_led.h>
#ifdef CONFIG_RED_LED
void red_led_on(void)
{
gpio_set_value(CONFIG_RED_LED, 1);
}
void red_led_off(void)
{
gpio_set_value(CONFIG_RED_LED, 0);
}
#endif
#ifdef CONFIG_GREEN_LED
void green_led_on(void)
{
gpio_set_value(CONFIG_GREEN_LED, 0);
}
void green_led_off(void)
{
gpio_set_value(CONFIG_GREEN_LED, 1);
}
#endif
#ifdef CONFIG_YELLOW_LED
void yellow_led_on(void)
{
gpio_set_value(CONFIG_YELLOW_LED, 0);
}
void yellow_led_off(void)
{
gpio_set_value(CONFIG_YELLOW_LED, 1);
}
#endif

19
arch/arm/mach-integrator/Kconfig
View File

@ -32,14 +32,18 @@ config CM920T
config CM926EJ_S
bool "Core Module for ARM926EJ-STM"
select CPU_ARM926EJS
select CM_TCRAM
config CM946ES
bool "Core Module for ARM946E-STM"
select CPU_ARM946ES
select CM_MULTIPLE_SSRAM
select CM_TCRAM
config CM1136
bool "Core Module for ARM1136JF-STM"
select CPU_ARM1136
select CM_TCRAM
endchoice
@ -56,4 +60,19 @@ config SYS_CONFIG_NAME
config SYS_MALLOC_F_LEN
default 0x2000
config CM_INIT
def_bool y
config CM_REMAP
def_bool y
config CM_SPD_DETECT
def_bool y
config CM_MULTIPLE_SSRAM
bool
config CM_TCRAM
bool
endmenu

4
arch/arm/mach-mvebu/Kconfig
View File

@ -90,6 +90,9 @@ config 88F6820
bool
select ARMADA_38X
config CUSTOMER_BOARD_SUPPORT
bool
choice
prompt "Armada XP/375/38x/3700/7K/8K board select"
optional
@ -173,6 +176,7 @@ config TARGET_THEADORABLE
config TARGET_CONTROLCENTERDC
bool "Support CONTROLCENTERDC"
select 88F6820
select CUSTOMER_BOARD_SUPPORT
config TARGET_X530
bool "Support Allied Telesis x530"

2
arch/arm/mach-mvebu/cpu.c
View File

@ -91,7 +91,7 @@ u32 get_boot_device(void)
* be done, via the bootrom error register. Here the
* MSB marks if the UART mode is active.
*/
val = readl(CONFIG_BOOTROM_ERR_REG);
val = readl(BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
if (boot_device == BOOTROM_ERR_MODE_UART)

2
arch/arm/mach-mvebu/include/mach/soc.h
View File

@ -125,7 +125,7 @@
#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6

1
arch/arm/mach-socfpga/misc_soc64.c
View File

@ -16,6 +16,7 @@
#include <errno.h>
#include <init.h>
#include <log.h>
#include <mach/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;

4
arch/arm/mach-tegra/Kconfig
View File

@ -164,6 +164,10 @@ config TEGRA_DISCONNECT_UDC_ON_BOOT
USB controller when U-Boot boots to avoid leaving a stale USB device
present.
config CI_UDC_HAS_HOSTPC
def_bool y
depends on CI_UDC && !TEGRA20
config SYS_MALLOC_F_LEN
default 0x1800

8
arch/microblaze/Kconfig
View File

@ -25,6 +25,14 @@ config TARGET_MICROBLAZE_GENERIC
endchoice
config DCACHE
bool "Enable dcache support"
default y
config ICACHE
bool "Enable icache support"
default y
source "board/xilinx/Kconfig"
source "board/xilinx/microblaze-generic/Kconfig"

3
arch/nds32/include/asm/arch-ag101/ag101.h
View File

@ -43,9 +43,6 @@
/* External AHB slave2 (FUSBH200) */
#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000
/* DEBUG LED */
#define CONFIG_DEBUG_LED 0x902FFFFC
/* APB Device definitions */
/* Power Management Unit */

2
arch/nds32/include/asm/arch-ag102/ag102.h
View File

@ -72,8 +72,6 @@
/* PWM - Pulse Width Modulator Controller */
#define CONFIG_FTPWM010_BASE 0x94F00000
/* Debug LED */
#define CONFIG_DEBUG_LED 0x902FFFFC
/* Power Management Unit */
#define CONFIG_FTPMU010_BASE 0x98100000

4
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -1,6 +1,10 @@
menu "mpc83xx CPU"
depends on MPC83xx
config DEFAULT_IMMR
hex
default 0xFF400000
config E300
def_bool y

4
board/AndesTech/adp-ag101p/Kconfig
View File

@ -1,5 +1,9 @@
if TARGET_ADP_AG101P
config DEBUG_LED
hex
default 0x902FFFFC
config SYS_CPU
default "n1213"

1
board/armltd/integrator/integrator.c
View File

@ -24,6 +24,7 @@
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <armcoremodule.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>

7
board/armltd/integrator/lowlevel_init.S
View File

@ -7,6 +7,7 @@
*/
#include <config.h>
#include <armcoremodule.h>
/* Reset using CM control register */
.global reset_cpu
@ -41,10 +42,6 @@ lowlevel_init:
/* set the desired CM specific value */
mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
orr r2,r2,#CMMASK_INIT_102
#else
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
@ -69,8 +66,6 @@ lowlevel_init:
#endif /* CMxx6 code */
#endif /* ARM102xxE value */
/* read CM_INIT */
mov r0, #CM_BASE
ldr r1, [r0, #OS_INIT]

1
board/atmel/at91sam9260ek/Makefile
View File

@ -8,4 +8,3 @@
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9260ek.o
obj-$(CONFIG_AT91_LED) += led.o

22
board/atmel/at91sam9260ek/led.c
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <status_led.h>
void coloured_LED_init(void)
{
/* Clock is enabled in board_early_init_f() */
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
}

1
board/atmel/at91sam9261ek/Makefile
View File

@ -8,4 +8,3 @@
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9261ek.o
obj-$(CONFIG_AT91_LED) += led.o

28
board/atmel/at91sam9261ek/led.c
View File

@ -1,28 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*/
#include <common.h>
#include <status_led.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <asm/io.h>
void coloured_LED_init(void)
{
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
}

1
board/atmel/at91sam9263ek/Makefile
View File

@ -8,4 +8,3 @@
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9263ek.o
obj-$(CONFIG_AT91_LED) += led.o

27
board/atmel/at91sam9263ek/led.c
View File

@ -1,27 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*/
#include <common.h>
#include <status_led.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/clk.h>
void coloured_LED_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
}

1
board/atmel/at91sam9m10g45ek/Makefile
View File

@ -8,4 +8,3 @@
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9m10g45ek.o
obj-(CONFIG_AT91_LED) += led.o

24
board/atmel/at91sam9m10g45ek/led.c
View File

@ -1,24 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*/
#include <common.h>
#include <status_led.h>
#include <asm/io.h>
#include <asm/arch/at91sam9g45.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
void coloured_LED_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIODE);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
}

1
board/atmel/at91sam9rlek/Makefile
View File

@ -8,4 +8,3 @@
# Lead Tech Design <www.leadtechdesign.com>
obj-y += at91sam9rlek.o
obj-$(CONFIG_AT91_LED) += led.o

26
board/atmel/at91sam9rlek/led.c
View File

@ -1,26 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*/
#include <common.h>
#include <status_led.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
void coloured_LED_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOD);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
}

8
board/freescale/common/Kconfig
View File

@ -99,3 +99,11 @@ config VOL_MONITOR_ISL68233_SET
functionality. It is used by the common VID driver.
endif
config FSL_QIXIS
bool "Enable QIXIS support"
config QIXIS_I2C_ACCESS
bool "Access to QIXIS is over i2c"
depends on FSL_QIXIS
default y

2
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -107,7 +107,7 @@ static void cpld_show(void)
in_8(&cpld_data->pcba_ver) & VERSION_MASK,
in_8(&cpld_data->vbank) & BANK_MASK);
#ifdef CONFIG_DEBUG
#ifdef DEBUG
printf("soft_mux_on =%x\n",
in_8(&cpld_data->soft_mux_on));
printf("cfg_rcw_src1 =%x\n",

1
board/ronetix/pm9261/Makefile
View File

@ -9,4 +9,3 @@
# Ilko Iliev <www.ronetix.at>
obj-y += pm9261.o
obj-$(CONFIG_RED_LED) += led.o

26
board/ronetix/pm9261/led.c
View File

@ -1,26 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
* Ilko Iliev <www.ronetix.at>
*/
#include <common.h>
#include <status_led.h>
#include <asm/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
void coloured_LED_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOC);
gpio_direction_output(CONFIG_RED_LED, 1);
gpio_direction_output(CONFIG_GREEN_LED, 1);
gpio_direction_output(CONFIG_YELLOW_LED, 1);
gpio_set_value(CONFIG_RED_LED, 0);
gpio_set_value(CONFIG_GREEN_LED, 1);
gpio_set_value(CONFIG_YELLOW_LED, 1);
}

1
board/ronetix/pm9263/Makefile
View File

@ -9,4 +9,3 @@
# Ilko Iliev <www.ronetix.at>
obj-y += pm9263.o
obj-$(CONFIG_AT91_LED) += led.o

24
board/ronetix/pm9263/led.c
View File

@ -1,24 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
* Ilko Iliev <www.ronetix.at>
*/
#include <common.h>
#include <status_led.h>
#include <asm/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
void coloured_LED_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOB);
gpio_direction_output(CONFIG_RED_LED, 1);
gpio_direction_output(CONFIG_GREEN_LED, 1);
gpio_set_value(CONFIG_RED_LED, 0);
gpio_set_value(CONFIG_GREEN_LED, 1);
}

24
board/siemens/corvus/board.c
View File

@ -52,8 +52,28 @@ static void corvus_request_gpio(void)
gpio_request(AT91_PIN_PD3, "USB1");
gpio_request(AT91_PIN_PB18, "SPICS1");
gpio_request(AT91_PIN_PB3, "SPICS0");
gpio_request(CONFIG_RED_LED, "red led");
gpio_request(CONFIG_GREEN_LED, "green led");
gpio_request(AT91_PIN_PD31, "red led"); /* this is the user1 led */
gpio_request(AT91_PIN_PD0, "green led"); /* this is the user2 led */
}
void red_led_on(void)
{
gpio_set_value(AT91_PIN_PD31, 1);
}
void red_led_off(void)
{
gpio_set_value(AT91_PIN_PD31, 0);
}
void green_led_on(void)
{
gpio_set_value(AT91_PIN_PD0, 0);
}
void green_led_off(void)
{
gpio_set_value(AT91_PIN_PD0, 1);
}
static void corvus_nand_hw_init(void)

19
board/st/stm32f429-discovery/led.c
View File

@ -8,30 +8,33 @@
#include <status_led.h>
#include <asm-generic/gpio.h>
#define RED_LED 110
#define GREEN_LED 109
void coloured_LED_init(void)
{
gpio_request(CONFIG_RED_LED, "red led");
gpio_direction_output(CONFIG_RED_LED, 0);
gpio_request(CONFIG_GREEN_LED, "green led");
gpio_direction_output(CONFIG_GREEN_LED, 0);
gpio_request(RED_LED, "red led");
gpio_direction_output(RED_LED, 0);
gpio_request(GREEN_LED, "green led");
gpio_direction_output(GREEN_LED, 0);
}
void red_led_off(void)
{
gpio_set_value(CONFIG_RED_LED, 0);
gpio_set_value(RED_LED, 0);
}
void green_led_off(void)
{
gpio_set_value(CONFIG_GREEN_LED, 0);
gpio_set_value(GREEN_LED, 0);
}
void red_led_on(void)
{
gpio_set_value(CONFIG_RED_LED, 1);
gpio_set_value(RED_LED, 1);
}
void green_led_on(void)
{
gpio_set_value(CONFIG_GREEN_LED, 1);
gpio_set_value(GREEN_LED, 1);
}

7
cmd/Kconfig
View File

@ -31,6 +31,13 @@ config CMDLINE_EDITING
Enable editing and History functions for interactive command line
input operations
config CMDLINE_PS_SUPPORT
bool "Enable support for changing the command prompt string at run-time"
depends on HUSH_PARSER
help
Only static string in the prompt is supported so far. The string is
obtained from environment variables PS1 and PS2.
config AUTO_COMPLETE
bool "Enable auto complete using TAB"
depends on CMDLINE

3
configs/T2080QDS_NAND_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
@ -63,6 +65,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

3
configs/T2080QDS_SDCARD_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
@ -61,6 +63,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

3
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@ -46,6 +48,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

3
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
@ -64,6 +66,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

3
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View File

@ -7,6 +7,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@ -44,6 +46,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

3
configs/T2080QDS_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@ -47,6 +49,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

2
configs/bk4r1_defconfig
View File

@ -17,6 +17,8 @@ CONFIG_ENV_OFFSET_REDUND=0x220000
CONFIG_TARGET_BK4R1=y
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3

2
configs/colibri_pxa270_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=262144
CONFIG_SYS_LOAD_ADDR=0xa0000000
CONFIG_TIMESTAMP=y
CONFIG_SYS_MONITOR_BASE=0x00000000

2
configs/colibri_vf_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_TARGET_COLIBRI_VF=y
CONFIG_SYS_MEMTEST_START=0x80010000
CONFIG_SYS_MEMTEST_END=0x87c00000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=520192
CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTCOMMAND=y

2
configs/ea-lpc3250devkitv2_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_EA_LPC3250DEVKITV2=y
CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=1048575
CONFIG_SYS_LOAD_ADDR=0x80100000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_AUTOBOOT is not set

2
configs/gardena-smart-gateway-mt7688_defconfig
View File

@ -22,6 +22,8 @@ CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=655360
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y

2
configs/guruplug_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=917504
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y

2
configs/j7200_evm_a72_defconfig
View File

@ -173,6 +173,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j7200_evm_r5_defconfig
View File

@ -134,6 +134,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j721e_evm_a72_defconfig
View File

@ -173,6 +173,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j721e_evm_r5_defconfig
View File

@ -127,6 +127,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j721e_hs_evm_a72_defconfig
View File

@ -145,6 +145,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j721e_hs_evm_r5_defconfig
View File

@ -114,6 +114,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j721s2_evm_a72_defconfig
View File

@ -181,6 +181,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/j721s2_evm_r5_defconfig
View File

@ -138,6 +138,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

2
configs/k2g_evm_defconfig
View File

@ -89,6 +89,8 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=384000000
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y

2
configs/k2g_hs_evm_defconfig
View File

@ -73,6 +73,8 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=384000000
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y

2
configs/linkit-smart-7688_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_MIPS_CACHE_DISABLE=y
CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_SYS_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y

1
configs/ls1012aqds_qspi_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y

1
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

1
configs/ls1012aqds_tfa_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
CONFIG_FSL_QIXIS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

2
configs/ls1021aqds_ddr4_nor_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff

2
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff

2
configs/ls1021aqds_nand_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y

2
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff

2
configs/ls1021aqds_nor_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff

2
configs/ls1021aqds_nor_lpuart_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff

1
configs/ls1021aqds_qspi_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff

2
configs/ls1021aqds_sdcard_ifc_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y

1
configs/ls1021aqds_sdcard_qspi_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y

2
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@ -49,6 +50,7 @@ CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/ls1028aqds_tfa_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@ -55,6 +56,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/ls1028aqds_tfa_lpuart_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart"
CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@ -54,6 +55,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

1
configs/ls1028ardb_tfa_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
CONFIG_FSL_QIXIS=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

2
configs/ls1043aqds_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1043aqds_lpuart_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1043aqds_nand_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y

2
configs/ls1043aqds_nor_ddr3_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

1
configs/ls1043aqds_qspi_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1043aqds_sdcard_ifc_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y

1
configs/ls1043aqds_sdcard_qspi_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y

1
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y

1
configs/ls1043aqds_tfa_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y

2
configs/ls1046aqds_SECURE_BOOT_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1046aqds_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1046aqds_lpuart_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1046aqds_nand_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y

1
configs/ls1046aqds_qspi_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x80000000

2
configs/ls1046aqds_sdcard_ifc_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_VOL_MONITOR_INA220=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y

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