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pm9261 converted to at91 soc access

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Signed-off-by: Asen Dimov <dimov@ronetix.at>
This commit is contained in:
Asen Dimov 2010-04-06 16:18:04 +03:00 committed by trix
parent 534864eff6
commit 9428d2f83c
3 changed files with 129 additions and 107 deletions
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18
board/ronetix/pm9261/led.c
View File

@ -26,19 +26,21 @@
#include <common.h> #include <common.h>
#include <asm/arch/at91sam9261.h> #include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h> #include <asm/arch/at91_pio.h>
#include <asm/arch/io.h> #include <asm/arch/io.h>
void coloured_LED_init(void) void coloured_LED_init(void)
{ {
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable clock */ /* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_pio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1); at91_set_pio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1); at91_set_pio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0); at91_set_pio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1); at91_set_pio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1); at91_set_pio_value(CONFIG_YELLOW_LED, 1);
} }

150
board/ronetix/pm9261/pm9261.c
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@ -27,13 +27,14 @@
#include <common.h> #include <common.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/arch/at91sam9261.h> #include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h> #include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <asm/arch/gpio.h> #include <asm/arch/at91_pio.h>
#include <asm/arch/io.h> #include <asm/arch/io.h>
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <lcd.h> #include <lcd.h>
@ -55,39 +56,48 @@ DECLARE_GLOBAL_DATA_PTR;
static void pm9261_nand_hw_init(void) static void pm9261_nand_hw_init(void)
{ {
unsigned long csa; unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable CS3 */ /* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA); csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
at91_sys_write(AT91_MATRIX_EBICSA, writel(csa, &matrix->csa);
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */ /* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3), writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); &smc->cs[3].setup);
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
at91_sys_write(AT91_SMC_CYCLE(3), &smc->cs[3].pulse);
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3), writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE | &smc->cs[3].cycle);
AT91_SMC_EXNWMODE_DISABLE |
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16 #ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 | AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */ #else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 | AT91_SMC_MODE_DBW_8 |
#endif #endif
AT91_SMC_TDF_(2)); AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
writel(1 << AT91SAM9261_ID_PIOA |
1 << AT91SAM9261_ID_PIOC,
&pmc->pcer);
/* Configure RDY/BSY */ /* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PA16, 1); at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */ /* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PC14, 1); at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
} }
#endif #endif
@ -95,23 +105,30 @@ static void pm9261_nand_hw_init(void)
#ifdef CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000
static void pm9261_dm9000_hw_init(void) static void pm9261_dm9000_hw_init(void)
{ {
at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Configure SMC CS2 for DM9000 */ /* Configure SMC CS2 for DM9000 */
at91_sys_write(AT91_SMC_SETUP(2), writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); &smc->cs[2].setup);
at91_sys_write(AT91_SMC_PULSE(2),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
at91_sys_write(AT91_SMC_CYCLE(2), &smc->cs[2].pulse);
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(2), writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE | &smc->cs[2].cycle);
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_TDF_(1)); AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
AT91_SMC_MODE_TDF_CYCLE(1),
&smc->cs[2].mode);
/* Configure Interrupt pin as input, no pull-up */ /* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PA24, 0); writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
} }
#endif #endif
@ -135,40 +152,42 @@ vidinfo_t panel_info = {
void lcd_enable(void) void lcd_enable(void)
{ {
at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
} }
void lcd_disable(void) void lcd_disable(void)
{ {
at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */ at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
} }
static void pm9261_lcd_hw_init(void) static void pm9261_lcd_hw_init(void)
{ {
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
gd->fb_base = AT91SAM9261_SRAM_BASE; gd->fb_base = AT91SAM9261_SRAM_BASE;
} }
@ -222,11 +241,14 @@ void lcd_show_board_info(void)
int board_init(void) int board_init(void)
{ {
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable Ctrlc */ /* Enable Ctrlc */
console_init_f(); console_init_f();
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); writel(1 << AT91SAM9261_ID_PIOA |
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); 1 << AT91SAM9261_ID_PIOC,
&pmc->pcer);
/* arch number of PM9261-Board */ /* arch number of PM9261-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9261; gd->bd->bi_arch_number = MACH_TYPE_PM9261;

68
include/configs/pm9261.h
View File

@ -28,8 +28,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
@ -51,26 +49,26 @@
/* clocks */ /* clocks */
/* CKGR_MOR - enable main osc. */ /* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL \ #define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \ (AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */ (255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \ #define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
AT91_PMC_OUT | \ AT91_PMC_PLLXR_OUT(3) | \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */ /* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \ #define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \ (AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_PRES_1 | \ AT91_PMC_MCKR_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \ AT91_PMC_MCKR_MDIV_2 | \
AT91_PMC_PDIV_1) AT91_PMC_MCKR_PLLADIV_1)
/* PCK/2 = MCK Master Clock from PLLA */ /* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \ #define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \ (AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_PRES_1 | \ AT91_PMC_MCKR_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \ AT91_PMC_MCKR_MDIV_2 | \
AT91_PMC_PDIV_1) AT91_PMC_MCKR_PLLADIV_1)
/* define PDC[31:16] as DATA[31:16] */ /* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
@ -79,7 +77,7 @@
/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL \ #define CONFIG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */ /* SDRAM */
/* SDRAMC_MR Mode register */ /* SDRAMC_MR Mode register */
@ -122,32 +120,32 @@
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \ #define CONFIG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL \ #define CONFIG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \ #define CONFIG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \ #define CONFIG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_DBW_16 | \ AT91_SMC_MODE_DBW_16 | \
AT91_SMC_TDFMODE | \ AT91_SMC_MODE_TDF | \
AT91_SMC_TDF_(6)) AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */ /* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \ #define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \ (AT91_RSTC_KEY | \
AT91_RSTC_PROCRST | \ AT91_RSTC_CR_PROCRST | \
AT91_RSTC_RSTTYP_WAKEUP | \ AT91_RSTC_MR_ERSTL(1) | \
AT91_RSTC_RSTTYP_WATCHDOG) AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */ /* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \ #define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_WDV | \ AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_WDDIS | \ AT91_WDT_MR_WDDIS | \
AT91_WDT_WDD) AT91_WDT_MR_WDD(0xfff))
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SETUP_MEMORY_TAGS 1
@ -180,9 +178,9 @@
/* LED */ /* LED */
#define CONFIG_AT91_LED #define CONFIG_AT91_LED
#define CONFIG_RED_LED AT91_PIN_PC12 #define CONFIG_RED_LED AT91_PIO_PORTC, 12
#define CONFIG_GREEN_LED AT91_PIN_PC13 #define CONFIG_GREEN_LED AT91_PIO_PORTC, 13
#define CONFIG_YELLOW_LED AT91_PIN_PC15 #define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15
#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTDELAY 3
@ -236,8 +234,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) #define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */ /* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
/* NOR flash */ /* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_SYS_FLASH_CFI 1