mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 12:08:19 +00:00
pm9261 converted to at91 soc access
Signed-off-by: Asen Dimov <dimov@ronetix.at>
This commit is contained in:
Asen Dimov
trix
parent
534864eff6
commit
9428d2f83c
@ -26,19 +26,21 @@
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#include <common.h>
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#include <asm/arch/at91sam9261.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/io.h>
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void coloured_LED_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
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writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer);
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at91_set_gpio_output(CONFIG_RED_LED, 1);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
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at91_set_pio_output(CONFIG_RED_LED, 1);
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at91_set_pio_output(CONFIG_GREEN_LED, 1);
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at91_set_pio_output(CONFIG_YELLOW_LED, 1);
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at91_set_gpio_value(CONFIG_RED_LED, 0);
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at91_set_gpio_value(CONFIG_GREEN_LED, 1);
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at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
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at91_set_pio_value(CONFIG_RED_LED, 0);
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at91_set_pio_value(CONFIG_GREEN_LED, 1);
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at91_set_pio_value(CONFIG_YELLOW_LED, 1);
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}
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@ -27,13 +27,14 @@
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#include <common.h>
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#include <asm/sizes.h>
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#include <asm/arch/at91sam9261.h>
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#include <asm/arch/at91sam9261_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#include <lcd.h>
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@ -55,39 +56,48 @@ DECLARE_GLOBAL_DATA_PTR;
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static void pm9261_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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writel(1 << AT91SAM9261_ID_PIOA |
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1 << AT91SAM9261_ID_PIOC,
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&pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(AT91_PIN_PA16, 1);
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(AT91_PIN_PC14, 1);
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at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
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at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
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}
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#endif
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@ -95,23 +105,30 @@ static void pm9261_nand_hw_init(void)
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#ifdef CONFIG_DRIVER_DM9000
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static void pm9261_dm9000_hw_init(void)
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{
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Configure SMC CS2 for DM9000 */
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at91_sys_write(AT91_SMC_SETUP(2),
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AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(2),
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
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AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
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at91_sys_write(AT91_SMC_CYCLE(2),
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AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
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at91_sys_write(AT91_SMC_MODE(2),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
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AT91_SMC_TDF_(1));
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[2].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
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&smc->cs[2].pulse);
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writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
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&smc->cs[2].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[2].mode);
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/* Configure Interrupt pin as input, no pull-up */
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at91_set_gpio_input(AT91_PIN_PA24, 0);
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writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
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at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
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}
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#endif
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@ -135,40 +152,42 @@ vidinfo_t panel_info = {
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */
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at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */
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at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
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}
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static void pm9261_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
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at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
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at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
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at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
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at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
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at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
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at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
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at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
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at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
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at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
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at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
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at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
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at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
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at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
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at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
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at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
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at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
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at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
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writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
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gd->fb_base = AT91SAM9261_SRAM_BASE;
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}
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@ -222,11 +241,14 @@ void lcd_show_board_info(void)
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int board_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable Ctrlc */
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console_init_f();
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
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writel(1 << AT91SAM9261_ID_PIOA |
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1 << AT91SAM9261_ID_PIOC,
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&pmc->pcer);
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/* arch number of PM9261-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9261;
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@ -28,8 +28,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
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@ -51,26 +49,26 @@
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/* clocks */
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/* CKGR_MOR - enable main osc. */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(AT91_PMC_MOR_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_OUT | \
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(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_PLLXR_OUT(3) | \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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(AT91_PMC_MCKR_CSS_SLOW | \
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AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2 | \
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AT91_PMC_MCKR_PLLADIV_1)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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(AT91_PMC_MCKR_CSS_PLLA | \
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AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2 | \
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AT91_PMC_MCKR_PLLADIV_1)
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
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@ -79,7 +77,7 @@
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/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
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#define CONFIG_SYS_MATRIX_EBICSA_VAL \
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(AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
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(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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@ -122,32 +120,32 @@
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
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AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
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(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
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AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
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AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
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(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
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AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
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(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
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AT91_SMC_DBW_16 | \
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||||
AT91_SMC_TDFMODE | \
|
||||
AT91_SMC_TDF_(6))
|
||||
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
|
||||
AT91_SMC_MODE_DBW_16 | \
|
||||
AT91_SMC_MODE_TDF | \
|
||||
AT91_SMC_MODE_TDF_CYCLE(6))
|
||||
|
||||
/* user reset enable */
|
||||
#define CONFIG_SYS_RSTC_RMR_VAL \
|
||||
(AT91_RSTC_KEY | \
|
||||
AT91_RSTC_PROCRST | \
|
||||
AT91_RSTC_RSTTYP_WAKEUP | \
|
||||
AT91_RSTC_RSTTYP_WATCHDOG)
|
||||
AT91_RSTC_CR_PROCRST | \
|
||||
AT91_RSTC_MR_ERSTL(1) | \
|
||||
AT91_RSTC_MR_ERSTL(2))
|
||||
|
||||
/* Disable Watchdog */
|
||||
#define CONFIG_SYS_WDTC_WDMR_VAL \
|
||||
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
|
||||
AT91_WDT_WDV | \
|
||||
AT91_WDT_WDDIS | \
|
||||
AT91_WDT_WDD)
|
||||
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
|
||||
AT91_WDT_MR_WDV(0xfff) | \
|
||||
AT91_WDT_MR_WDDIS | \
|
||||
AT91_WDT_MR_WDD(0xfff))
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
@ -180,9 +178,9 @@
|
||||
|
||||
/* LED */
|
||||
#define CONFIG_AT91_LED
|
||||
#define CONFIG_RED_LED AT91_PIN_PC12
|
||||
#define CONFIG_GREEN_LED AT91_PIN_PC13
|
||||
#define CONFIG_YELLOW_LED AT91_PIN_PC15
|
||||
#define CONFIG_RED_LED AT91_PIO_PORTC, 12
|
||||
#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13
|
||||
#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
@ -236,8 +234,8 @@
|
||||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
|
||||
/* our CLE is AD21 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
|
||||
|
||||
/* NOR flash */
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user