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stm32mp1: ram: remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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@ -116,24 +116,6 @@
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DDR_MR3
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DDR_MR3
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>;
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>;
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#ifdef DDR_PHY_CAL_SKIP
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st,phy-cal = <
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DDR_DX0DLLCR
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DDR_DX0DQTR
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DDR_DX0DQSTR
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DDR_DX1DLLCR
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DDR_DX1DQTR
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DDR_DX1DQSTR
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DDR_DX2DLLCR
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DDR_DX2DQTR
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DDR_DX2DQSTR
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DDR_DX3DLLCR
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DDR_DX3DQTR
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DDR_DX3DQSTR
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>;
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#endif
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status = "okay";
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status = "okay";
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};
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};
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};
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};
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@ -224,18 +206,6 @@
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#undef DDR_ODTCR
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#undef DDR_ODTCR
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#undef DDR_ZQ0CR1
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#undef DDR_ZQ0CR1
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#undef DDR_DX0GCR
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#undef DDR_DX0GCR
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#undef DDR_DX0DLLCR
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#undef DDR_DX0DQTR
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#undef DDR_DX0DQSTR
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#undef DDR_DX1GCR
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#undef DDR_DX1GCR
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#undef DDR_DX1DLLCR
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#undef DDR_DX1DQTR
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#undef DDR_DX1DQSTR
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#undef DDR_DX2GCR
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#undef DDR_DX2GCR
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#undef DDR_DX2DLLCR
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#undef DDR_DX2DQTR
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#undef DDR_DX2DQSTR
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#undef DDR_DX3GCR
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#undef DDR_DX3GCR
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#undef DDR_DX3DLLCR
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#undef DDR_DX3DQTR
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#undef DDR_DX3DQSTR
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@ -100,20 +100,8 @@
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#define DDR_ODTCR 0x00010000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE80
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#define DDR_DX2GCR 0x0000CE80
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE80
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#define DDR_DX3GCR 0x0000CE80
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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#include "stm32mp15-ddr.dtsi"
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@ -100,20 +100,8 @@
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#define DDR_ODTCR 0x00010000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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#include "stm32mp15-ddr.dtsi"
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@ -101,20 +101,8 @@
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#define DDR_ODTCR 0x00010000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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#include "stm32mp15-ddr.dtsi"
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@ -101,20 +101,8 @@
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#define DDR_ODTCR 0x00010000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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#include "stm32mp15-ddr.dtsi"
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@ -101,20 +101,8 @@
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#define DDR_ODTCR 0x00010000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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#include "stm32mp15-ddr.dtsi"
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#define DDR_ODTCR 0x00010000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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#include "stm32mp15-ddr.dtsi"
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@ -128,23 +128,6 @@ phyc attributes:
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MR2
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MR2
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MR3
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MR3
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- st,phy-cal : phy cal depending of calibration or tuning of DDR
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This parameter is optional; when it is absent the built-in PHY
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calibration is done.
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for STM32MP15x: 12 values are requested in this order
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DX0DLLCR
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DX0DQTR
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DX0DQSTR
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DX1DLLCR
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DX1DQTR
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DX1DQSTR
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DX2DLLCR
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DX2DQTR
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DX2DQSTR
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DX3DLLCR
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DX3DQTR
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DX3DQSTR
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Example:
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Example:
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/ {
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/ {
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@ -280,21 +263,6 @@ Example:
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0x00000000 /*MR3*/
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0x00000000 /*MR3*/
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>;
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>;
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st,phy-cal = <
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0x40000000 /*DX0DLLCR*/
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0xFFFFFFFF /*DX0DQTR*/
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0x3DB02000 /*DX0DQSTR*/
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0x40000000 /*DX1DLLCR*/
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0xFFFFFFFF /*DX1DQTR*/
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0x3DB02000 /*DX1DQSTR*/
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0x40000000 /*DX2DLLCR*/
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0xFFFFFFFF /*DX2DQTR*/
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0x3DB02000 /*DX2DQSTR*/
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0x40000000 /*DX3DLLCR*/
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0xFFFFFFFF /*DX3DQTR*/
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0x3DB02000 /*DX3DQSTR*/
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>;
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status = "okay";
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status = "okay";
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};
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};
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};
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};
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@ -68,7 +68,6 @@ struct reg_desc {
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#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
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#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
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#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
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#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
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#define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
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#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
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#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
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static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
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static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
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@ -178,22 +177,6 @@ static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
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DDRPHY_REG_TIMING(mr3),
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DDRPHY_REG_TIMING(mr3),
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};
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};
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#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
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static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
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DDRPHY_REG_CAL(dx0dllcr),
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DDRPHY_REG_CAL(dx0dqtr),
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DDRPHY_REG_CAL(dx0dqstr),
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DDRPHY_REG_CAL(dx1dllcr),
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DDRPHY_REG_CAL(dx1dqtr),
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DDRPHY_REG_CAL(dx1dqstr),
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DDRPHY_REG_CAL(dx2dllcr),
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DDRPHY_REG_CAL(dx2dqtr),
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DDRPHY_REG_CAL(dx2dqstr),
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DDRPHY_REG_CAL(dx3dllcr),
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DDRPHY_REG_CAL(dx3dqtr),
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DDRPHY_REG_CAL(dx3dqstr),
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};
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/**************************************************************
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/**************************************************************
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* DYNAMIC REGISTERS: only used for debug purpose (read/modify)
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* DYNAMIC REGISTERS: only used for debug purpose (read/modify)
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**************************************************************/
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**************************************************************/
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@ -218,12 +201,24 @@ static const struct reg_desc ddrphy_dyn[] = {
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DDRPHY_REG_DYN(zq0sr1),
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DDRPHY_REG_DYN(zq0sr1),
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DDRPHY_REG_DYN(dx0gsr0),
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DDRPHY_REG_DYN(dx0gsr0),
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DDRPHY_REG_DYN(dx0gsr1),
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DDRPHY_REG_DYN(dx0gsr1),
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DDRPHY_REG_DYN(dx0dllcr),
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DDRPHY_REG_DYN(dx0dqtr),
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DDRPHY_REG_DYN(dx0dqstr),
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DDRPHY_REG_DYN(dx1gsr0),
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DDRPHY_REG_DYN(dx1gsr0),
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DDRPHY_REG_DYN(dx1gsr1),
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DDRPHY_REG_DYN(dx1gsr1),
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DDRPHY_REG_DYN(dx1dllcr),
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DDRPHY_REG_DYN(dx1dqtr),
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DDRPHY_REG_DYN(dx1dqstr),
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DDRPHY_REG_DYN(dx2gsr0),
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DDRPHY_REG_DYN(dx2gsr0),
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DDRPHY_REG_DYN(dx2gsr1),
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DDRPHY_REG_DYN(dx2gsr1),
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DDRPHY_REG_DYN(dx2dllcr),
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DDRPHY_REG_DYN(dx2dqtr),
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DDRPHY_REG_DYN(dx2dqstr),
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DDRPHY_REG_DYN(dx3gsr0),
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DDRPHY_REG_DYN(dx3gsr0),
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DDRPHY_REG_DYN(dx3gsr1),
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DDRPHY_REG_DYN(dx3gsr1),
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DDRPHY_REG_DYN(dx3dllcr),
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DDRPHY_REG_DYN(dx3dqtr),
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DDRPHY_REG_DYN(dx3dqstr),
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};
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};
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#define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
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#define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
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@ -240,7 +235,6 @@ enum reg_type {
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REG_MAP,
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REG_MAP,
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REGPHY_REG,
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REGPHY_REG,
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REGPHY_TIMING,
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REGPHY_TIMING,
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REGPHY_CAL,
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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/* dynamic registers => managed in driver or not changed,
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/* dynamic registers => managed in driver or not changed,
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* can be dumped in interactive mode
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* can be dumped in interactive mode
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@ -264,8 +258,6 @@ struct ddr_reg_info {
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enum base_type base;
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enum base_type base;
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};
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};
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#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
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const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
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const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
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[REG_REG] = {
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[REG_REG] = {
|
||||||
"static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
|
"static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
|
||||||
@ -279,8 +271,6 @@ const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
|
|||||||
"static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
|
"static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
|
||||||
[REGPHY_TIMING] = {
|
[REGPHY_TIMING] = {
|
||||||
"timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
|
"timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
|
||||||
[REGPHY_CAL] = {
|
|
||||||
"cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
|
|
||||||
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
|
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
|
||||||
[REG_DYN] = {
|
[REG_DYN] = {
|
||||||
"dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
|
"dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
|
||||||
@ -456,9 +446,6 @@ static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
|
|||||||
case REGPHY_TIMING:
|
case REGPHY_TIMING:
|
||||||
par_addr = (u32)&config->p_timing;
|
par_addr = (u32)&config->p_timing;
|
||||||
break;
|
break;
|
||||||
case REGPHY_CAL:
|
|
||||||
par_addr = (u32)&config->p_cal;
|
|
||||||
break;
|
|
||||||
case REG_DYN:
|
case REG_DYN:
|
||||||
case REGPHY_DYN:
|
case REGPHY_DYN:
|
||||||
case REG_TYPE_NB:
|
case REG_TYPE_NB:
|
||||||
@ -774,8 +761,6 @@ start:
|
|||||||
*/
|
*/
|
||||||
set_reg(priv, REGPHY_REG, &config->p_reg);
|
set_reg(priv, REGPHY_REG, &config->p_reg);
|
||||||
set_reg(priv, REGPHY_TIMING, &config->p_timing);
|
set_reg(priv, REGPHY_TIMING, &config->p_timing);
|
||||||
if (config->p_cal_present)
|
|
||||||
set_reg(priv, REGPHY_CAL, &config->p_cal);
|
|
||||||
|
|
||||||
if (INTERACTIVE(STEP_PHY_INIT))
|
if (INTERACTIVE(STEP_PHY_INIT))
|
||||||
goto start;
|
goto start;
|
||||||
@ -810,36 +795,32 @@ start:
|
|||||||
|
|
||||||
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
||||||
|
|
||||||
if (config->p_cal_present) {
|
log_debug("DDR DQS training : ");
|
||||||
log_debug("DDR DQS training skipped.\n");
|
|
||||||
} else {
|
|
||||||
log_debug("DDR DQS training : ");
|
|
||||||
/* 8. Disable Auto refresh and power down by setting
|
/* 8. Disable Auto refresh and power down by setting
|
||||||
* - RFSHCTL3.dis_au_refresh = 1
|
* - RFSHCTL3.dis_au_refresh = 1
|
||||||
* - PWRCTL.powerdown_en = 0
|
* - PWRCTL.powerdown_en = 0
|
||||||
* - DFIMISC.dfiinit_complete_en = 0
|
* - DFIMISC.dfiinit_complete_en = 0
|
||||||
*/
|
*/
|
||||||
stm32mp1_refresh_disable(priv->ctl);
|
stm32mp1_refresh_disable(priv->ctl);
|
||||||
|
|
||||||
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
|
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
|
||||||
* not done => keep the programed value in PGCR
|
* not done => keep the programed value in PGCR
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* 10. configure PUBL PIR register to specify which training step to run */
|
/* 10. configure PUBL PIR register to specify which training step to run */
|
||||||
/* RVTRN is excuted only on LPDDR2/LPDDR3 */
|
/* RVTRN is excuted only on LPDDR2/LPDDR3 */
|
||||||
if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
|
if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
|
||||||
pir = DDRPHYC_PIR_QSTRN;
|
pir = DDRPHYC_PIR_QSTRN;
|
||||||
else
|
else
|
||||||
pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN;
|
pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN;
|
||||||
stm32mp1_ddrphy_init(priv->phy, pir);
|
stm32mp1_ddrphy_init(priv->phy, pir);
|
||||||
|
|
||||||
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
|
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
|
||||||
ddrphy_idone_wait(priv->phy);
|
ddrphy_idone_wait(priv->phy);
|
||||||
|
|
||||||
/* 12. set back registers in step 8 to the orginal values if desidered */
|
/* 12. set back registers in step 8 to the orginal values if desidered */
|
||||||
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
|
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
|
||||||
config->c_reg.pwrctl);
|
config->c_reg.pwrctl);
|
||||||
} /* if (config->p_cal_present) */
|
|
||||||
|
|
||||||
/* enable uMCTL2 AXI port 0 and 1 */
|
/* enable uMCTL2 AXI port 0 and 1 */
|
||||||
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
|
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
|
||||||
|
@ -140,21 +140,6 @@ struct stm32mp1_ddrphy_timing {
|
|||||||
u32 mr3;
|
u32 mr3;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct stm32mp1_ddrphy_cal {
|
|
||||||
u32 dx0dllcr;
|
|
||||||
u32 dx0dqtr;
|
|
||||||
u32 dx0dqstr;
|
|
||||||
u32 dx1dllcr;
|
|
||||||
u32 dx1dqtr;
|
|
||||||
u32 dx1dqstr;
|
|
||||||
u32 dx2dllcr;
|
|
||||||
u32 dx2dqtr;
|
|
||||||
u32 dx2dqstr;
|
|
||||||
u32 dx3dllcr;
|
|
||||||
u32 dx3dqtr;
|
|
||||||
u32 dx3dqstr;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct stm32mp1_ddr_info {
|
struct stm32mp1_ddr_info {
|
||||||
const char *name;
|
const char *name;
|
||||||
u32 speed; /* in kHZ */
|
u32 speed; /* in kHZ */
|
||||||
@ -169,8 +154,6 @@ struct stm32mp1_ddr_config {
|
|||||||
struct stm32mp1_ddrctrl_perf c_perf;
|
struct stm32mp1_ddrctrl_perf c_perf;
|
||||||
struct stm32mp1_ddrphy_reg p_reg;
|
struct stm32mp1_ddrphy_reg p_reg;
|
||||||
struct stm32mp1_ddrphy_timing p_timing;
|
struct stm32mp1_ddrphy_timing p_timing;
|
||||||
struct stm32mp1_ddrphy_cal p_cal;
|
|
||||||
bool p_cal_present;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
|
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
|
||||||
|
@ -111,7 +111,7 @@ static void stm32mp1_do_usage(void)
|
|||||||
"help displays help\n"
|
"help displays help\n"
|
||||||
"info displays DDR information\n"
|
"info displays DDR information\n"
|
||||||
"info <param> <val> changes DDR information\n"
|
"info <param> <val> changes DDR information\n"
|
||||||
" with <param> = step, name, size, speed or cal\n"
|
" with <param> = step, name, size or speed\n"
|
||||||
"freq displays the DDR PHY frequency in kHz\n"
|
"freq displays the DDR PHY frequency in kHz\n"
|
||||||
"freq <freq> changes the DDR PHY frequency\n"
|
"freq <freq> changes the DDR PHY frequency\n"
|
||||||
"param [type|reg] prints input parameters\n"
|
"param [type|reg] prints input parameters\n"
|
||||||
@ -132,7 +132,7 @@ static void stm32mp1_do_usage(void)
|
|||||||
"\nwith for [type|reg]:\n"
|
"\nwith for [type|reg]:\n"
|
||||||
" all registers if absent\n"
|
" all registers if absent\n"
|
||||||
" <type> = ctl, phy\n"
|
" <type> = ctl, phy\n"
|
||||||
" or one category (static, timing, map, perf, cal, dyn)\n"
|
" or one category (static, timing, map, perf, dyn)\n"
|
||||||
" <reg> = name of the register\n"
|
" <reg> = name of the register\n"
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -165,7 +165,6 @@ static void stm32mp1_do_info(struct ddr_info *priv,
|
|||||||
printf("name = %s\n", config->info.name);
|
printf("name = %s\n", config->info.name);
|
||||||
printf("size = 0x%x\n", config->info.size);
|
printf("size = 0x%x\n", config->info.size);
|
||||||
printf("speed = %d kHz\n", config->info.speed);
|
printf("speed = %d kHz\n", config->info.speed);
|
||||||
printf("cal = %d\n", config->p_cal_present);
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -214,16 +213,6 @@ static void stm32mp1_do_info(struct ddr_info *priv,
|
|||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
if (!strcmp(argv[1], "cal")) {
|
|
||||||
if (strict_strtoul(argv[2], 10, &value) < 0 ||
|
|
||||||
(value != 0 && value != 1)) {
|
|
||||||
printf("invalid value %s\n", argv[2]);
|
|
||||||
} else {
|
|
||||||
config->p_cal_present = value;
|
|
||||||
printf("cal = %d\n", config->p_cal_present);
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
printf("argument %s invalid\n", argv[1]);
|
printf("argument %s invalid\n", argv[1]);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -95,26 +95,22 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
|
|||||||
{ .name = x, \
|
{ .name = x, \
|
||||||
.offset = offsetof(struct stm32mp1_ddr_config, y), \
|
.offset = offsetof(struct stm32mp1_ddr_config, y), \
|
||||||
.size = sizeof(config.y) / sizeof(u32), \
|
.size = sizeof(config.y) / sizeof(u32), \
|
||||||
.present = z, \
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
|
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
|
||||||
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
|
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
|
||||||
#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
|
|
||||||
|
|
||||||
const struct {
|
const struct {
|
||||||
const char *name; /* name in DT */
|
const char *name; /* name in DT */
|
||||||
const u32 offset; /* offset in config struct */
|
const u32 offset; /* offset in config struct */
|
||||||
const u32 size; /* size of parameters */
|
const u32 size; /* size of parameters */
|
||||||
bool * const present; /* presence indication for opt */
|
|
||||||
} param[] = {
|
} param[] = {
|
||||||
CTL_PARAM(reg),
|
CTL_PARAM(reg),
|
||||||
CTL_PARAM(timing),
|
CTL_PARAM(timing),
|
||||||
CTL_PARAM(map),
|
CTL_PARAM(map),
|
||||||
CTL_PARAM(perf),
|
CTL_PARAM(perf),
|
||||||
PHY_PARAM(reg),
|
PHY_PARAM(reg),
|
||||||
PHY_PARAM(timing),
|
PHY_PARAM(timing)
|
||||||
PHY_PARAM_OPT(cal)
|
|
||||||
};
|
};
|
||||||
|
|
||||||
config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
|
config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
|
||||||
@ -133,25 +129,11 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
|
|||||||
param[idx].size);
|
param[idx].size);
|
||||||
dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
|
dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
|
||||||
param[idx].name, param[idx].size, ret);
|
param[idx].name, param[idx].size, ret);
|
||||||
if (ret &&
|
if (ret) {
|
||||||
(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
|
|
||||||
dev_err(dev, "Cannot read %s, error=%d\n",
|
dev_err(dev, "Cannot read %s, error=%d\n",
|
||||||
param[idx].name, ret);
|
param[idx].name, ret);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
if (param[idx].present) {
|
|
||||||
/* save presence of optional parameters */
|
|
||||||
*param[idx].present = true;
|
|
||||||
if (ret == -FDT_ERR_NOTFOUND) {
|
|
||||||
*param[idx].present = false;
|
|
||||||
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
|
|
||||||
/* reset values if used later */
|
|
||||||
memset((void *)((u32)&config +
|
|
||||||
param[idx].offset),
|
|
||||||
0, param[idx].size * sizeof(u32));
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_get_by_name(dev, "axidcg", &axidcg);
|
ret = clk_get_by_name(dev, "axidcg", &axidcg);
|
||||||
|
Loading…
x
Reference in New Issue
Block a user