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gpio: axp: Remove virtual VBUS enable GPIO
Now that this functionality is modeled using the device tree and regulator uclass, the named GPIO is not referenced anywhere. Remove it, along with the rest of the support for AXP virtual GPIOs. Series-to: Andre Przywara <andre.przywara@arm.com> Series-to: Jagan Teki <jagan@amarulasolutions.com> Series-cc: Chen-Yu Tsai <wens@csie.org> Series-cc: Hans de Goede <hdegoede@redhat.com> Series-cc: Icenowy Zheng <icenowy@aosc.xyz> Series-cc: Maxime Ripard <mripard@kernel.org> Series-cc: Adam Sampson <ats@offog.org> Series-cc: Stefan Roese <sr@denx.de> Series-cc: u-boot@lists.denx.de Cover-letter: sunxi: Control USB VBUS supplies via DT regulators This series converts sunxi boards from controlling VBUS suppllies using GPIO name strings in Kconfig to using regulator devices probed via the devicetree. ARCH_SUNXI already implies DM_REGULATOR_FIXED, so the only new driver needed is for the AXP PMIC drivevbus regulator. This is part 2 of 3 for removing the PHY driver's GPIO Kconfig options. Part 1 was here[1]. Part 3 will finish converting the VBUS/ID detection GPIOs; it requires adding some missing DT properties to a couple of boards, so it will have to wait for at least the next DT sync from Linux. I tried to verify (by inspection) every board affected by this change, but there is some possibility that this could break some boards. See the commit message for patch 3. I have CCed some relevant board maintaners; please test this patch series if you have the opportunity. [1]: https://lore.kernel.org/u-boot/20230122234623.1636-1-samuel@sholland.org/ END Signed-off-by: Samuel Holland <samuel@sholland.org>
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@ -16,6 +16,9 @@
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#include <errno.h>
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#include <sunxi_gpio.h>
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#define AXP_GPIO_PREFIX "AXP0-"
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#define AXP_GPIO_COUNT 4
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static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
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static u8 axp_get_gpio_ctrl_reg(unsigned pin)
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@ -47,28 +50,14 @@ static int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
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static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
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int val)
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{
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__maybe_unused int ret;
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u8 reg;
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switch (pin) {
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#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
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/* Only available on later PMICs */
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case SUNXI_GPIO_AXP0_VBUS_ENABLE:
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ret = pmic_bus_clrbits(AXP_MISC_CTRL,
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AXP_MISC_CTRL_N_VBUSEN_FUNC);
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if (ret)
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return ret;
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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return axp_gpio_set_value(dev, pin, val);
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
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AXP_GPIO_CTRL_OUTPUT_LOW);
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}
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return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
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AXP_GPIO_CTRL_OUTPUT_LOW);
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}
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static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
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@ -76,25 +65,16 @@ static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
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u8 reg, val, mask;
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int ret;
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switch (pin) {
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#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
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/* Only available on later PMICs */
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case SUNXI_GPIO_AXP0_VBUS_ENABLE:
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ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
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mask = AXP_VBUS_IPSOUT_DRIVEBUS;
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break;
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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ret = pmic_bus_read(AXP_GPIO_STATE, &val);
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mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
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}
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ret = pmic_bus_read(AXP_GPIO_STATE, &val);
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if (ret)
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return ret;
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mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
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return (val & mask) ? 1 : 0;
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}
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@ -102,25 +82,12 @@ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
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{
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u8 reg;
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switch (pin) {
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#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
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/* Only available on later PMICs */
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case SUNXI_GPIO_AXP0_VBUS_ENABLE:
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if (val)
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return pmic_bus_setbits(AXP_VBUS_IPSOUT,
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AXP_VBUS_IPSOUT_DRIVEBUS);
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else
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return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
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AXP_VBUS_IPSOUT_DRIVEBUS);
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
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AXP_GPIO_CTRL_OUTPUT_LOW);
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}
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return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
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AXP_GPIO_CTRL_OUTPUT_LOW);
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}
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static const struct dm_gpio_ops gpio_axp_ops = {
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@ -135,8 +102,8 @@ static int gpio_axp_probe(struct udevice *dev)
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* Tell the uclass how many GPIOs we have */
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uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
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uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
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uc_priv->bank_name = AXP_GPIO_PREFIX;
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uc_priv->gpio_count = AXP_GPIO_COUNT;
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return 0;
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}
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@ -247,15 +247,7 @@ int sunxi_name_to_gpio(const char *name)
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{
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unsigned int gpio;
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int ret;
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#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
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char lookup[8];
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if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
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sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
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SUNXI_GPIO_AXP0_VBUS_ENABLE);
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name = lookup;
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}
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#endif
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ret = gpio_lookup_name(name, NULL, NULL, &gpio);
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return ret ? ret : gpio;
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@ -53,10 +53,6 @@
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#ifdef CONFIG_AXP221_POWER
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#define AXP_POWER_STATUS 0x00
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#define AXP_POWER_STATUS_ALDO_IN BIT(0)
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#define AXP_VBUS_IPSOUT 0x30
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#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
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#define AXP_MISC_CTRL 0x8f
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#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
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#define AXP_GPIO0_CTRL 0x90
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#define AXP_GPIO1_CTRL 0x92
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#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
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@ -47,10 +47,6 @@
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#ifdef CONFIG_AXP809_POWER
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#define AXP_POWER_STATUS 0x00
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#define AXP_POWER_STATUS_ALDO_IN BIT(0)
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#define AXP_VBUS_IPSOUT 0x30
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#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
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#define AXP_MISC_CTRL 0x8f
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#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
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#define AXP_GPIO0_CTRL 0x90
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#define AXP_GPIO1_CTRL 0x92
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#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
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@ -61,10 +61,6 @@
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#ifdef CONFIG_AXP818_POWER
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#define AXP_POWER_STATUS 0x00
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#define AXP_POWER_STATUS_ALDO_IN BIT(0)
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#define AXP_VBUS_IPSOUT 0x30
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#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
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#define AXP_MISC_CTRL 0x8f
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#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
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#define AXP_GPIO0_CTRL 0x90
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#define AXP_GPIO1_CTRL 0x92
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#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
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@ -82,7 +82,6 @@ enum sunxi_gpio_number {
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SUNXI_GPIO_L_START = 352,
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SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
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SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
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SUNXI_GPIO_AXP0_START = 1024,
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};
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/* SUNXI GPIO number definitions */
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@ -99,8 +98,6 @@ enum sunxi_gpio_number {
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#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
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#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
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#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
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/* GPIO pin function config */
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#define SUNXI_GPIO_INPUT 0
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#define SUNXI_GPIO_OUTPUT 1
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@ -185,11 +182,6 @@ enum sunxi_gpio_number {
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#define SUNXI_GPIO_PULL_UP 1
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#define SUNXI_GPIO_PULL_DOWN 2
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/* Virtual AXP0 GPIOs */
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#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
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#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
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#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
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struct sunxi_gpio_plat {
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void *regs;
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char bank_name[3];
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