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phy: cadence: Sierra: Add PHY PCS common register configurations

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Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This commit is contained in:
Swapnil Jakhade 2022-01-28 13:41:44 +05:30 committed by Tom Rini
parent 445c8cf89b
commit 990ce535eb
1 changed files with 38 additions and 0 deletions
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38
drivers/phy/cadence/phy-cadence-sierra.c
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@ -150,6 +150,7 @@
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000 #define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe #define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID 0x00007364 #define SIERRA_MACRO_ID 0x00007364
@ -251,6 +252,8 @@ struct cdns_sierra_data {
u32 id_value; u32 id_value;
u8 block_offset_shift; u8 block_offset_shift;
u8 reg_offset_shift; u8 reg_offset_shift;
struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE]; [NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@ -321,6 +324,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
enum cdns_sierra_phy_type phy_type = ins->phy_type; enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs; const struct cdns_reg_pairs *reg_pairs;
struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap; struct regmap *regmap = phy->regmap;
u32 num_regs; u32 num_regs;
int i, j; int i, j;
@ -332,6 +336,16 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
/* PHY PCS common registers configurations */
pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pcs_cmn_vals) {
reg_pairs = pcs_cmn_vals->reg_pairs;
num_regs = pcs_cmn_vals->num_regs;
regmap = phy->regmap_phy_pcs_common_cdb;
for (i = 0; i < num_regs; i++)
regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
}
/* PMA common registers configurations */ /* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) { if (pma_cmn_vals) {
@ -887,6 +901,16 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0; return 0;
} }
/* PCIE PHY PCS common configuration */
static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
{0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
};
static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
.reg_pairs = pcie_phy_pcs_cmn_regs,
.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
};
/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@ -1038,6 +1062,13 @@ static const struct cdns_sierra_data cdns_map_sierra = {
.id_value = SIERRA_MACRO_ID, .id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x2, .block_offset_shift = 0x2,
.reg_offset_shift = 0x2, .reg_offset_shift = 0x2,
.pcs_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
},
},
.pma_cmn_vals = { .pma_cmn_vals = {
[TYPE_PCIE] = { [TYPE_PCIE] = {
[TYPE_NONE] = { [TYPE_NONE] = {
@ -1068,6 +1099,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
.id_value = SIERRA_MACRO_ID, .id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x0, .block_offset_shift = 0x0,
.reg_offset_shift = 0x1, .reg_offset_shift = 0x1,
.pcs_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
},
},
.pma_cmn_vals = { .pma_cmn_vals = {
[TYPE_PCIE] = { [TYPE_PCIE] = {
[TYPE_NONE] = { [TYPE_NONE] = {