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mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT node
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi file. It also adds the L2C DT node, as this is referenced by the DDR driver. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -72,6 +72,23 @@
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<0x0300e 4>, <0x0300f 4>;
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<0x0300e 4>, <0x0300f 4>;
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};
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};
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l2c: l2c@1180080000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-7xxx-l2c";
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reg = <0x11800 0x80000000 0x0 0x01000000>;
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u-boot,dm-pre-reloc;
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};
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lmc: lmc@1180088000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-7xxx-ddr4";
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reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs
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u-boot,dm-pre-reloc;
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l2c-handle = <&l2c>;
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};
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reset: reset@1180006001600 {
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reset: reset@1180006001600 {
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compatible = "mrvl,cn7xxx-rst";
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compatible = "mrvl,cn7xxx-rst";
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reg = <0x11800 0x06001600 0x0 0x200>;
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reg = <0x11800 0x06001600 0x0 0x200>;
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